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"A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector ..."

Zhao Zhang et al. (2020)

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DOI: 10.1109/JSSC.2020.3005780

access: closed

type: Journal Article

metadata version: 2023-09-29

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Zhao Zhang, Guang Zhu, Can Wang, Li Wang, C. Patrick Yue:
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator. IEEE J. Solid State Circuits 55(10): 2734-2746 (2020)

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