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ORCIDFrancisco J. Cazorla
Francisco Javier Cazorla-Almeida
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- affiliation: Barcelona Supercomputing Center, Spain
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2020 – today
- 2024
[j70]Alejandro J. Calderón
, Leonidas Kosmidis, Carlos F. Nicolás, Francisco J. Cazorla:
XeroZerox: Analysis and Optimization of GPU Memory Management for High-Integrity Autonomous Systems. IEEE Access 12: 77141-77155 (2024)- [j69]Jon Pérez-Cerrolaza, Jaume Abella, Markus Borg, Carlo Donzella, Jesús Cerquides, Francisco J. Cazorla, Cristofer Englund, Markus Tauber, George Nikolakopoulos, Jose Luis Flores:
Artificial Intelligence for Safety-Critical Systems in Industrial and Transportation Domains: A Survey. ACM Comput. Surv. 56(7): 176:1-176:40 (2024) - [c178]Alejandro Serrano-Cases, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+. DSD 2024: 282-290 - [c177]Roger Pujol, Sergi Vilardell, Enrico Mezzetti, Mohamed Hassan, Jaume Abella, Francisco J. Cazorla:
Event Monitor Validation in High-Integrity Systems. DSD 2024: 394-402 - [c176]Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
TAP: Task-Aware Profiling on Integrated Systems. DSD 2024: 559-567 - [c175]Adrià Aldomà, Axel Brando, Francisco J. Cazorla, Jaume Abella:
Safety-Relevant AI-Based System Robustification with Neural Network Ensembles. IOLTS 2024: 1-3 - [c174]Javier Barrera, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Increasing Testing Robustness of GPU Software in Embedded Critical Systems. SAC 2024: 452-453 - 2023
- [j68]Jon Pérez-Cerrolaza, Francisco J. Cazorla, Jaume Abella:
Uncertainty Management in Dependable and Intelligent Embedded Software. Computer 56(3): 114-117 (2023) - [j67]Axel Brando, Isabel Serra, Enrico Mezzetti, Francisco J. Cazorla, Jon Pérez-Cerrolaza, Jaume Abella:
On Neural Networks Redundancy and Diversity for Their Use in Safety-Critical Systems. Computer 56(5): 41-50 (2023) - [j66]Jon Pérez-Cerrolaza, Jaume Abella, Leonidas Kosmidis, Alejandro J. Calderón, Francisco J. Cazorla, Jose Luis Flores:
GPU Devices for Safety-Critical Systems: A Survey. ACM Comput. Surv. 55(7): 147:1-147:37 (2023) - [j65]Martí Caro, Hamid Tabani, Jaume Abella, Francesc Moll, Enric Morancho, Ramon Canal, Josep Altet, Antonio Calomarde, Francisco J. Cazorla, Antonio Rubio, Pau Fontova, Jordi Fornt:
An automotive case study on the limits of approximation for object detection. J. Syst. Archit. 138: 102872 (2023) - [j64]Miguel Alcon, Axel Brando, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Main sources of variability and non-determinism in AD software: taxonomy and prospects to handle them. Real Time Syst. 59(3): 438-478 (2023) - [j63]Miguel Alcon, Hamid Tabani, Jaume Abella, Francisco J. Cazorla:
Dynamic and execution views to improve validation, testing, and optimization of autonomous driving software. Softw. Qual. J. 31(2): 405-439 (2023) - [j62]Roger Pujol, Josep Jorba, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Vector Extensions in COTS Processors to Increase Guaranteed Performance in Real-Time Systems. ACM Trans. Embed. Comput. Syst. 22(2): 21:1-21:26 (2023) - [j61]Jordi Cardona, Carles Hernández, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla:
Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems. ACM Trans. Design Autom. Electr. Syst. 28(3): 43:1-43:34 (2023) - [c173]Axel Brando, Isabel Serra, Enrico Mezzetti, Francisco J. Cazorla, Jaume Abella:
Standardizing the Probabilistic Sources of Uncertainty for the sake of Safety Deep Learning. SafeAI@AAAI 2023 - [c172]Jaume Abella, Jon Pérez, Cristofer Englund, Bahram Zonooz, Gabriele Giordana, Carlo Donzella, Francisco J. Cazorla, Enrico Mezzetti, Isabel Serra, Axel Brando, Irune Agirre, Fernando Eizaguirre, Thanh Hai Bui, Elahe Arani, Fahad Sarfraz, Ajay Balasubramaniam, Ahmed Badar, Ilaria Bloise, Lorenzo Feruglio, Ilaria Cinelli, Davide Brighenti, Davide Cunial:
SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI. DATE 2023: 1-6 - [c171]Sergio Garcia-Esteban, Alejandro Serrano-Cases, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla:
Quasi Isolation QoS Setups to Control MPSoC Contention in Integrated Software Architectures. ECRTS 2023: 5:1-5:25 - [c170]Fabio Pavanello, Cédric Marchand, Ian O'Connor, Régis Orobtchouk, Fabien Mandorlo, Xavier Letartre, Sébastien Cueff, Elena-Ioana Vatajelu, Giorgio Di Natale, Benoit Cluzel, Aurelien Coillet, Benoît Charbonnier, Pierre Noe, Frantisek Kavan, Martin Zoldak, Michal Szaj, Peter Bienstman, Thomas Van Vaerenbergh, Ulrich Rührmair, Paulo F. Flores, Luís Guerra e Silva, Ricardo Chaves, Luís Miguel Silveira, Mariano Ceccato, Dimitris Gizopoulos, George Papadimitriou, Vasileios Karakostas, Axel Brando, Francisco J. Cazorla, Ramon Canal, Pau Closas, Adria Gusi-Amigo, Paolo Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, Stefano Di Carlo, Alessandro Savino:
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. ETS 2023: 1-6 - [c169]Marcel Sarraseca, Sergi Alcaide, Francisco Fuentes, Juan Carlos Rodriguez, Feng Chang, Ilham Lasfar, Ramon Canal, Francisco J. Cazorla, Jaume Abella:
SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core. IOLTS 2023: 1-7 - [c168]Asier Fernández de Lecea, Mohamed Hassan, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems. RTSS 2023: 265-278 - [c167]Nikolaos Andriotis, Alejandro Serrano-Cases, Sergi Alcaide, Jaume Abella, Francisco J. Cazorla, Yang Peng, Andrea Baldovin, Michael Paulitsch, Vladimir Tsymbal:
A Software-Only Approach to Enable Diverse Redundancy on Intel GPUs for Safety-Related Kernels. SAC 2023: 451-460 - [c166]Roger Pujol, Mohamed Hassan, Hamid Tabani, Jaume Abella, Francisco Javier Cazorla-Almeida:
Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems. SAC 2023: 461-470 - [c165]Jeremy Jens Giesen León, Enrico Mezzetti, Jaume Abella, Francisco Javier Cazorla-Almeida:
ASCOM: Affordable Sequence-aware COntention Modeling in Crossbar-based MPSoCs. SAC 2023: 471-474 - [i6]Martí Caro, Hamid Tabani, Jaume Abella, Francesc Moll, Enric Morancho, Ramon Canal, Josep Altet, Antonio Calomarde, Francisco J. Cazorla, Antonio Rubio, Pau Fontova, Jordi Fornt:
An Automotive Case Study on the Limits of Approximation for Object Detection. CoRR abs/2304.06327 (2023) - [i5]Fabio Pavanello, Cédric Marchand, Ian O'Connor, Régis Orobtchouk, Fabien Mandorlo, Xavier Letartre, Sébastien Cueff, Elena-Ioana Vatajelu, Giorgio Di Natale, Benoit Cluzel, Aurelien Coillet, Benoît Charbonnier, Pierre Noe, Frantisek Kavan, Martin Zoldak, Michal Szaj, Peter Bienstman, Thomas Van Vaerenbergh, Ulrich Rührmair, Paulo F. Flores, Luís Guerra e Silva, Ricardo Chaves, Luís Miguel Silveira, Mariano Ceccato, Dimitris Gizopoulos, George Papadimitriou, Vasileios Karakostas, Axel Brando, Francisco J. Cazorla, Ramon Canal, Pau Closas, Adria Gusi-Amigo, Paolo Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, Stefano Di Carlo, Alessandro Savino:
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. CoRR abs/2305.03139 (2023) - [i4]Jaume Abella, Francisco J. Cazorla, Sergi Alcaide, Michael Paulitsch, Yang Peng, Inês Pinto Gouveia:
Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains. CoRR abs/2307.11940 (2023) - [i3]Marcel Sarraseca, Sergi Alcaide, Francisco Fuentes, Juan Carlos Rodriguez, Feng Chang, Ilham Lasfar, Ramon Canal, Francisco J. Cazorla, Jaume Abella:
SafeLS: Toward Building a Lockstep NOEL-V Core. CoRR abs/2307.15436 (2023) - 2022
- [j60]Hamid Tabani, Roger Pujol, Miguel Alcon, Joan Moya, Jaume Abella, Francisco J. Cazorla:
ADBench: benchmarking autonomous driving systems. Computing 104(3): 481-502 (2022) - [c164]Axel Brando, Isabel Serra, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Using Quantile Regression in Neural Networks for Contention Prediction in Multicore Processors. ECRTS 2022: 4:1-4:25 - [c163]Sergi Vilardell, Isabel Serra, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla, Joan del Castillo:
Using Markov's Inequality with Power-Of-k Function for Probabilistic WCET Estimation. ECRTS 2022: 20:1-20:24 - [c162]Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Jaume Abella, Francisco J. Cazorla:
Contention Tracking in GPU Last-Level Cache. ICCD 2022: 76-79 - [c161]Javier Fernández, Irune Agirre, Jon Pérez-Cerrolaza, Jaume Abella, Francisco J. Cazorla:
A Methodology for Selective Protection of Matrix Multiplications: A Diagnostic Coverage and Performance Trade-off for CNNs Executed on GPUs. ICSRS 2022: 9-18 - 2021
- [j59]Jon Pérez-Cerrolaza, Roman Obermaisser, Jaume Abella, Francisco J. Cazorla, Kim Grüttner, Irune Agirre, Hamidreza Ahmadian, Imanol Allende:
Multi-core Devices for Safety-critical Systems: A Survey. ACM Comput. Surv. 53(4): 79:1-79:38 (2021) - [j58]Hamid Tabani, Fabio Mazzocchetti, Pedro Benedicte, Jaume Abella, Francisco J. Cazorla:
Performance Analysis and Optimization Opportunities for NVIDIA Automotive GPUs. J. Parallel Distributed Comput. 152: 21-32 (2021) - [j57]Javier Fernández, Jon Pérez, Irune Agirre, Imanol Allende, Jaume Abella, Francisco J. Cazorla:
Towards functional safety compliance of matrix-matrix multiplication for machine learning-based autonomous systems. J. Syst. Archit. 121: 102298 (2021) - [j56]Irune Agirre, Irune Yarza, Imanol Mugarza, Jacopo Binchi, Peio Onaindia, Tomaso Poggi, Francisco J. Cazorla, Leonidas Kosmidis, Kim Grüttner, Patrick Uven, Mohammed Abuteir, Jan Loewe, Juan M. Orbegozo, Stefania Botta:
Safe and secure software updates on high-performance mixed-criticality systems: The UP2DATE approach. Microprocess. Microsystems 87: 104351 (2021) - [j55]Gabriel Fernandez, Jaume Abella, Guillem Bernat, Francisco J. Cazorla:
Surrogate Applications for Early Design Stage Multicore Contention Modeling. IEEE Trans. Emerg. Top. Comput. 9(1): 109-116 (2021) - [j54]David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices. IEEE Trans. Sustain. Comput. 6(3): 522-530 (2021) - [c160]Roger Pujol, Hamid Tabani, Jaume Abella, Mohamed Hassan, Francisco J. Cazorla:
Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence. DATE 2021: 1162-1165 - [c159]Miguel Alcon, Hamid Tabani, Jaume Abella, Francisco J. Cazorla:
Enabling Unit Testing of Already-Integrated AI Software Systems: The Case of Apollo for Autonomous Driving. DSD 2021: 426-433 - [c158]Alejandro Serrano-Cases, Juan M. Reina, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla:
Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC. ECRTS 2021: 3:1-3:26 - [c157]Kazi Asifuzzaman, Mohamed Abuelala, Mohamed Hassan, Francisco J. Cazorla:
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems. ICCAD 2021: 1-9 - [c156]Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
PRL: Standardizing Performance Monitoring Library for High-Integrity Real-Time Systems. ICCD 2021: 344-348 - [c155]Sergi Vilardell, Isabel Serra, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
MUCH: exploiting pairwise hardware event monitor correlations for improved timing analysis of complex MPSoCs. SAC 2021: 511-520 - [i2]Hamid Tabani, Fabio Mazzocchetti, Pedro Benedicte, Jaume Abella, Francisco J. Cazorla:
Performance Analysis and Optimization Opportunities for NVIDIA Automotive GPUs. CoRR abs/2104.07735 (2021) - [i1]Leonidas Kosmidis, Iván Rodriguez, Álvaro Jover, Sergi Alcaide, Jérôme Lachaize, Jaume Abella, Olivier Notebaert, Francisco J. Cazorla, David Steenari:
GPU4S: Embedded GPUs in Space - Latest Project Updates. CoRR abs/2109.11074 (2021) - 2020
- [j53]Leonidas Kosmidis, Iván Rodriguez, Álvaro Jover, Sergi Alcaide, Jérôme Lachaize, Jaume Abella, Olivier Notebaert, Francisco J. Cazorla, David Steenari:
GPU4S: Embedded GPUs in space - Latest project updates. Microprocess. Microsystems 77: 103143 (2020) - [j52]Sergi Vilardell, Isabel Serra, Roberto Santalla, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3662-3673 (2020) - [j51]Alejandro J. Calderón, Leonidas Kosmidis, Carlos F. Nicolás, Francisco J. Cazorla, Peio Onaindia:
GMAI: Understanding and Exploiting the Internals of GPU Resource Allocation in Critical Systems. ACM Trans. Embed. Comput. Syst. 19(5): 34:1-34:23 (2020) - [c154]Iván Rodriguez, Leonidas Kosmidis, Olivier Notebaert, Francisco J. Cazorla, David Steenari:
An On-board Algorithm Implementation on an Embedded GPU: A Space Case Study. DATE 2020: 1718-1719 - [c153]Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luís Villa:
An Academic RISC-V Silicon Implementation Based on Open-Source Components. DCIS 2020: 1-6 - [c152]Irune Agirre, Peio Onaindia, Tomaso Poggi, Irune Yarza, Francisco J. Cazorla, Leonidas Kosmidis, Kim Grüttner, Mohammed Abuteir, Jan Loewe, Juan M. Orbegozo, Stefania Botta:
UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems. DSD 2020: 344-351 - [c151]Xavier Palomo, Mikel Fernández, Sylvain Girbal, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla, Laurent Rioux:
Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study. ECRTS 2020: 15:1-15:25 - [c150]Hamid Tabani, Roger Pujol, Jaume Abella, Francisco J. Cazorla:
A Cross-Layer Review of Deep Learning Frameworks to Ease Their Optimization and Reuse. ISORC 2020: 144-145 - [c149]Jeremy Giesen, Pedro Benedicte, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP). RTAS 2020: 253-266 - [c148]Miguel Alcon, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Timing of Autonomous Driving Software: Problem Analysis and Prospects for Future Solutions. RTAS 2020: 267-280 - [c147]Sergi Vilardell, Isabel Serra, Hamid Tabani, Jaume Abella, Joan del Castillo, Francisco J. Cazorla:
CleanET: enabling timing validation for complex automotive systems. SAC 2020: 554-563 - [c146]Hamid Tabani, Matteo Fusi, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla:
IntPred: flexible, fast, and accurate object detection for autonomous driving systems. SAC 2020: 564-571 - [c145]Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Enrico Mezzetti, Jaume Abella, Mikel Fernández, Guillem Bernat, Francisco J. Cazorla:
On the reliability of hardware event monitors in MPSoCs for critical domains. SAC 2020: 580-589 - [c144]Miguel Alcon, Hamid Tabani, Jaume Abella, Leonidas Kosmidis, Francisco J. Cazorla:
En-Route: on enabling resource usage testing for autonomous driving frameworks. SAC 2020: 1953-1962
2010 – 2019
- 2019
- [j50]Francisco J. Cazorla, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, Tullio Vardanega:
Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey. ACM Comput. Surv. 52(1): 14:1-14:35 (2019) - [j49]David Trilla, Francisco J. Cazorla, Carles Hernández, Jaume Abella:
Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors. IEEE Des. Test 36(6): 39-47 (2019) - [j48]Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Time-Randomized Wormhole NoCs for Critical Applications. ACM J. Emerg. Technol. Comput. Syst. 15(1): 3:1-3:23 (2019) - [j47]Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Locality-aware cache random replacement policies. J. Syst. Archit. 93: 48-61 (2019) - [j46]Suzana Milutinovic, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Increasing the Reliability of Software Timing Analysis for Cache-Based Processors. IEEE Trans. Computers 68(6): 836-851 (2019) - [c143]Pedro Benedicte, Jaume Abella, Carles Hernández, Enrico Mezzetti, Francisco J. Cazorla:
Towards limiting the impact of timing anomalies in complex real-time processors. ASP-DAC 2019: 27-32 - [c142]Hamid Tabani, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla, Guillem Bernat:
Assessing the Adherence of an Industrial Autonomous Driving Framework to ISO 26262 Software Guidelines. DAC 2019: 9 - [c141]Jordi Cardona, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement. DATE 2019: 710-715 - [c140]Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache. DATE 2019: 818-823 - [c139]Enrico Mezzetti, Luca Barbina, Jaume Abella, Stefania Botta, Francisco J. Cazorla:
AURIX TC277 Multicore Contention Model Integration for Automotive Applications. DATE 2019: 1202-1203 - [c138]Mikel Fernández, Gabriel Fernandez, Jaume Abella, Francisco J. Cazorla:
Multicore Early Design Stage Guaranteed Performance Estimates for the Space Domain. DATE 2019: 1206-1207 - [c137]Leonidas Kosmidis, Jérôme Lachaize, Jaume Abella, Olivier Notebaert, Francisco J. Cazorla, David Steenari:
GPU4S: Embedded GPUs in Space. DSD 2019: 399-405 - [c136]David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior. DSD 2019: 538-545 - [c135]David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation. DSD 2019: 601-605 - [c134]Roger Pujol, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Generating and Exploiting Deep Learning Variants to Increase Heterogeneous Resource Utilization in the NVIDIA Xavier. ECRTS 2019: 23:1-23:23 - [c133]Alejandro J. Calderón, Leonidas Kosmidis, Carlos F. Nicolás, Francisco J. Cazorla, Peio Onaindia:
Understanding and Exploiting the Internals of GPU Resource Allocation for Critical Systems. ICCAD 2019: 1-8 - [c132]Sergi Vilardell, Isabel Serra, Jaume Abella, Joan del Castillo, Francisco J. Cazorla:
Software Timing Analysis for Complex Hardware with Survivability and Risk Analysis. ICCD 2019: 227-236 - [c131]Kazi Asifuzzaman, Mikel Fernández, Petar Radojkovic, Jaume Abella, Francisco J. Cazorla:
STT-MRAM for real-time embedded systems: performance and WCET implications. MEMSYS 2019: 195-205 - [c130]Xavier Palomo, Enrico Mezzetti, Jaume Abella, Reinder J. Bril, Francisco J. Cazorla:
Accurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems. RTAS 2019: 15-28 - [c129]Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla:
On assessing the viability of probabilistic scheduling with dependent tasks. SAC 2019: 625-634 - [c128]Fabio Mazzocchetti, Pedro Benedicte, Hamid Tabani, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla:
Performance Analysis and Optimization of Automotive GPUs. SBAC-PAD 2019: 96-103 - [c127]Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Enrique Fernández, Francisco J. Cazorla:
ePAPI: Performance Application Programming Interface for Embedded Platforms. WCET 2019: 3:1-3:13 - 2018
- [j45]Francisco J. Cazorla, Jaume Abella, Enrico Mezzetti, Carles Hernández, Tullio Vardanega, Guillem Bernat:
Reconciling Time Predictability and Performance in Future Computing Systems. IEEE Des. Test 35(2): 48-56 (2018) - [j44]Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla:
High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V. IEEE Micro 38(1): 56-65 (2018) - [j43]Sergi Alcaide, Leonidas Kosmidis, Hamid Tabani, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain. IEEE Micro 38(6): 46-55 (2018) - [j42]Jordi Cardona, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2451-2461 (2018) - [j41]Irune Agirre, Francisco J. Cazorla, Jaume Abella, Carles Hernández, Enrico Mezzetti, Mikel Azkarate-askatsua, Tullio Vardanega:
Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262. IEEE Trans. Reliab. 67(3): 1314-1327 (2018) - [c126]Enrique Díaz, Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla:
Modelling multicore contention on the AURIXTM TC27x. DAC 2018: 97:1-97:6 - [c125]David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Cache side-channel attacks and time-predictability in high-performance critical real-time systems. DAC 2018: 98:1-98:6 - [c124]Suzana Milutinovic, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla:
Measurement-based cache representativeness on multipath programs. DAC 2018: 123:1-123:6 - [c123]Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Design and integration of hierarchical-placement multi-level caches for real-time systems. DATE 2018: 455-460 - [c122]Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems. ECRTS 2018: 3:1-3:22 - [c121]Leonidas Kosmidis, Cristian Maxim, Victor Jégu, Francis Vatrinet, Francisco J. Cazorla:
Industrial experiences with resource management under software randomization in ARINC653 avionics environments. ICCAD 2018: 108 - [c120]Jordi Cardona, Carles Hernández, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores. RTSS 2018: 265-276 - [c119]Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
RPR: a random replacement policy with limited pathological replacements. SAC 2018: 593-600 - [c118]Gabriel Fernandez, Francisco J. Cazorla, Jaume Abella, Sylvain Girbal:
Assessing Time Predictability Features of ARM Big. LITTLE Multicores. SBAC-PAD 2018: 258-261 - 2017
- [j40]Suzana Milutinovic, Jaume Abella, Francisco J. Cazorla:
On the assessment of probabilistic WCET estimates reliability for arbitrary programs. EURASIP J. Embed. Syst. 2017: 28 (2017) - [j39]Joan del Castillo, Maria Padilla, Jaume Abella, Francisco J. Cazorla:
Execution time distributions in embedded safety-critical systems using extreme value theory. Int. J. Data Anal. Tech. Strateg. 9(4): 348-361 (2017) - [j38]Milos Panic, Jaume Abella, Eduardo Quiñones, Carles Hernández, Theo Ungerer, Francisco J. Cazorla:
Adapting TDMA arbitration for measurement-based probabilistic timing analysis. Microprocess. Microsystems 52: 188-201 (2017) - [j37]Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla:
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration. IEEE Trans. Computers 66(4): 586-600 (2017) - [j36]Jaume Abella, Maria Padilla, Joan del Castillo, Francisco J. Cazorla:
Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation. ACM Trans. Design Autom. Electr. Syst. 22(4): 72:1-72:29 (2017) - [c117]Enrique Díaz, Mikel Fernández, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding. Ada-Europe 2017: 102-118 - [c116]Suzana Milutinovic, Jaume Abella, Irune Agirre, Mikel Azkarate-askasua, Enrico Mezzetti, Tullio Vardanega, Francisco J. Cazorla:
Software Time Reliability in the Presence of Cache Memories. Ada-Europe 2017: 233-249 - [c115]Fabrice Cros, Leonidas Kosmidis, Franck Wartel, David Morales, Jaume Abella, Ian Broster, Francisco J. Cazorla:
Dynamic software randomisation: Lessons learnec from an aerospace case study. DATE 2017: 103-108 - [c114]Mikel Fernández, David Morales, Leonidas Kosmidis, Alen Bardizbanyan, Ian Broster, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Paulo Machado, Luca Fossati:
Probabilistic timing analysis on time-randomized platforms for the space domain. DATE 2017: 738-739 - [c113]Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Design and implementation of a fair credit-based bandwidth sharing scheme for buses. DATE 2017: 926-929 - [c112]Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis. DSD 2017: 440-444 - [c111]Carles Hernández, Jaume Abella, Francisco J. Cazorla, Alen Bardizbanyan, Jan Andersson, Fabrice Cros, Franck Wartel:
Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study. ECRTS 2017: 16:1-16:23 - [c110]Enrico Mezzetti, Mikel Fernández, Alen Bardizbanyan, Irune Agirre, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla:
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application. RTAS 2017: 163-174 - [c109]Enrico Mezzetti, Jaume Abella, Carles Hernández, Francisco J. Cazorla:
Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling. RTSS 2017: 357-359 - [c108]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems. SBAC-PAD 2017: 73-80 - [c107]Irune Agirre, Jaume Abella, Mikel Azkarate-askasua, Francisco J. Cazorla:
On the tailoring of CAST-32A certification guidance to real COTS multicore architectures. SIES 2017: 1-8 - [c106]Suzana Milutinovic, Enrico Mezzetti, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla:
On uses of extreme value theory fit for industrial-quality WCET analysis. SIES 2017: 1-6 - [c105]David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Modelling bus contention during system early design stages. SIES 2017: 1-8 - [e3]William D. Gropp, Pete Beckman, Zhiyuan Li, Francisco J. Cazorla:
Proceedings of the International Conference on Supercomputing, ICS 2017, Chicago, IL, USA, June 14-16, 2017. ACM 2017, ISBN 978-1-4503-5020-4 [contents] - 2016
- [j35]Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Carles Hernández, Andrea Gianarro, Ian Broster, Francisco J. Cazorla:
Fitting processor architectures for measurement-based probabilistic timing analysis. Microprocess. Microsystems 47: 287-302 (2016) - [j34]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero:
Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Trans. Archit. Code Optim. 12(4): 60:1-60:26 (2016) - [j33]Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach. IEEE Trans. Computers 65(1): 256-269 (2016) - [j32]Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel G. Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernández, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka:
Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore. ACM Trans. Embed. Comput. Syst. 15(3): 53:1-53:27 (2016) - [j31]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems. ACM Trans. Design Autom. Electr. Syst. 22(1): 16:1-16:26 (2016) - [c104]Carles Hernández, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J. Cazorla:
Random modulo: a new processor cache design for real-time critical systems. DAC 2016: 29:1-29:6 - [c103]Sebastian Kehr, Milos Panic, Eduardo Quiñones, Bert Böddeker, Jorge Becerril Sandoval, Jaume Abella, Francisco J. Cazorla, Günter Schäfer:
Supertask: Maximizing runnable-level parallelism in AUTOSAR applications. DATE 2016: 25-30 - [c102]Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla:
Improving performance guarantees in wormhole mesh NoC designs. DATE 2016: 1485-1488 - [c101]Francisco J. Cazorla, Jaume Abella, Jan Andersson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-askasua, Franck Wartel, Liliana Cucu, Fabrice Cros, Glenn Farrall, Adriana Gogonel, Andrea Gianarro, Benoit Triquet, Carles Hernández, Code Lo, Cristian Maxim, David Morales, Eduardo Quiñones, Enrico Mezzetti, Leonidas Kosmidis, Irune Agirre, Mikel Fernández, Mladen Slijepcevic, Philippa Conmy, Walid Talaboulma:
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis. DSD 2016: 276-285 - [c100]Mladen Slijepcevic, Mikel Fernández, Carles Hernández, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems. DSD 2016: 404-412 - [c99]Leonidas Kosmidis, Roberto Vargas, David Morales, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla:
TASA: toolchain-agnostic static software randomisation for critical real-time systems. ICCAD 2016: 59 - [c98]Pedro Benedicte, Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla:
A confidence assessment of WCET estimates for software time randomized caches. INDIN 2016: 90-97 - [c97]David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Resilient random modulo cache memories for probabilistically-analyzable real-time systems. IOLTS 2016: 27-32 - [c96]Suzana Milutinovic, Jaume Abella, Francisco J. Cazorla:
Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns. ISORC 2016: 142-149 - [c95]Milos Panic, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla:
Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems. RTAS 2016: 267-278 - [c94]David Trilla, Javier Jalle, Mikel Fernández, Jaume Abella, Francisco J. Cazorla:
Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems. RTAS 2016: 305-316 - [c93]Irune Agirre, Mikel Azkarate-askasua, Asier Larrucea, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla:
Automotive Safety Concept Definition for Mixed-Criticality Integration on a COTS Multicore. SAFECOMP Workshops 2016: 273-285 - [c92]Pedro Benedicte, Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla:
Modelling the confidence of timing analysis for time randomised caches. SIES 2016: 141-148 - [c91]Javier Jalle, Mikel Fernández, Jaume Abella, Jan Andersson, Mathieu Patte, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
Contention-aware performance monitoring counte support for real-time MPSoCs. SIES 2016: 262-271 - [c90]Javier Jalle, Eduardo Quiñones, Jaume Abella, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems. SIES 2016: 272-279 - [c89]Enrique Díaz, Jaume Abella, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-askasua, Tullio Vardanega, Francisco J. Cazorla:
Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis. WCET 2016: 1:1-1:11 - [c88]Leonidas Kosmidis, Davide Compagnin, David Morales, Enrico Mezzetti, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla:
Measurement-Based Timing Analysis of the AURIX Caches. WCET 2016: 9:1-9:11 - 2015
- [j30]Enrico Mezzetti, Marco Ziccardi, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems. Leibniz Trans. Embed. Syst. 2(1): 01:1-01:10 (2015) - [c87]Irune Agirre, Mikel Azkarate-askasua, Asier Larrucea, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla:
A Safety Concept for a Railway Mixed-Criticality Embedded System Based on Multicore Partitioning. CIT/IUCC/DASC/PICom 2015: 1780-1787 - [c86]Suzana Milutinovic, Jaume Abella, Damien Hardy, Eduardo Quiñones, Isabelle Puaut, Francisco J. Cazorla:
Speeding up Static Probabilistic Timing Analysis. ARCS 2015: 236-247 - [c85]Suzana Milutinovic, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla:
PACO: fast average-performance estimation for time-randomized caches. DAC 2015: 124:1-124:6 - [c84]Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla:
Increasing confidence on measurement-based contention bounds for real-time round-robin buses. DAC 2015: 125:1-125:6 - [c83]Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla:
Resource usage templates and signatures for COTS multicore processors. DAC 2015: 155:1-155:6 - [c82]Franck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zoë R. Stephenson, Benoit Triquet, Eduardo Quiñones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega, Francisco J. Cazorla:
Timing analysis of an avionics case study on complex hardware/software platforms. DATE 2015: 397-402 - [c81]Milos Panic, Jaume Abella, Carles Hernández, Eduardo Quiñones, Theo Ungerer, Francisco J. Cazorla:
Enabling TDMA Arbitration in the Context of MBPTA. DSD 2015: 462-469 - [c80]Irune Agirre, Mikel Azkarate-askasua, Carles Hernández, Jaume Abella, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla:
IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. DSD 2015: 677-684 - [c79]Milos Panic, Eduardo Quiñones, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores. DSD 2015: 685-692 - [c78]Víctor Jiménez, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell, Francisco J. Cazorla, Mateo Valero:
Increasing multicore system efficiency through intelligent bandwidth shifting. HPCA 2015: 39-50 - [c77]Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Tullio Vardanega, Francisco J. Cazorla:
Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors. ISORC 2015: 208-217 - [c76]Marco Ziccardi, Enrico Mezzetti, Tullio Vardanega, Jaume Abella, Francisco J. Cazorla:
EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis. RTSS 2015: 338-349 - [c75]Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
Introduction to partial time composability for COTS multicores. SAC 2015: 1955-1956 - [c74]Jaume Abella, Carles Hernández, Eduardo Quiñones, Francisco J. Cazorla, Philippa Ryan Conmy, Mikel Azkarate-askasua, Jon Pérez, Enrico Mezzetti, Tullio Vardanega:
WCET analysis methods: Pitfalls and challenges on their trustworthiness. SIES 2015: 39-48 - [e2]Francisco J. Cazorla:
15th International Workshop on Worst-Case Execution Time Analysis, WCET 2015, July 7, 2015, Lund, Sweden. OASIcs 47, Schloss Dagstuhl - Leibniz-Zentrum für Informatik 2015, ISBN 978-3-939897-95-8 [contents] - 2014
- [j29]Qixiao Liu, Víctor Jiménez, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Per-task Energy Accounting in Computing Systems. IEEE Comput. Archit. Lett. 13(2): 85-88 (2014) - [j28]Mladen Slijepcevic, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments. IEEE Micro 34(6): 8-19 (2014) - [j27]Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Efficient Cache Designs for Probabilistically Analysable Real-Time Systems. IEEE Trans. Computers 63(12): 2998-3011 (2014) - [j26]Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation. ACM Trans. Design Autom. Electr. Syst. 20(1): 10:1-10:25 (2014) - [j25]Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell, Bruce G. Mealey:
Adaptive Prefetching on POWER7: Improving Performance and Power Consumption. ACM Trans. Parallel Comput. 1(1): 4:1-4:25 (2014) - [c73]Milos Panic, Sebastian Kehr, Eduardo Quiñones, Bert Böddeker, Jaume Abella, Francisco J. Cazorla:
RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores. CODES+ISSS 2014: 29:1-29:10 - [c72]Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Glenn Farrall, Franck Wartel, Francisco J. Cazorla:
Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware. DAC 2014: 22:1-22:6 - [c71]Mladen Slijepcevic, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems. DAC 2014: 198:1-198:6 - [c70]Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Bus designs for time-probabilistic multicore processors. DATE 2014: 1-6 - [c69]Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Ian Broster, Francisco J. Cazorla:
Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture. DSD 2014: 401-410 - [c68]Jaume Abella, Eduardo Quiñones, Franck Wartel, Tullio Vardanega, Francisco J. Cazorla:
Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA. ECRTS 2014: 255-265 - [c67]Jaume Abella, Damien Hardy, Isabelle Puaut, Eduardo Quiñones, Francisco J. Cazorla:
On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques. ECRTS 2014: 266-275 - [c66]Leonidas Kosmidis, Jaume Abella, Franck Wartel, Eduardo Quiñones, Antoine Colin, Francisco J. Cazorla:
PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis. ECRTS 2014: 276-287 - [c65]Milos Panic, Eduardo Quiñones, Pavel G. Zaykov, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Parallel many-core avionics systems. EMSOFT 2014: 26:1-26:10 - [c64]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
DReAM: Per-Task DRAM Energy Metering in Multicore Systems. Euro-Par 2014: 111-123 - [c63]Javier Jalle, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
AHRB: A high-performance time-composable AMBA AHB bus. RTAS 2014: 225-236 - [c62]Javier Jalle, Eduardo Quiñones, Jaume Abella, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study. RTSS 2014: 207-217 - [c61]Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Christine Rochange, Tullio Vardanega, Francisco J. Cazorla:
Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art. WCET 2014: 31-42 - 2013
- [j24]Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Mateo Valero:
Fair CPU time accounting in CMP+SMT processors. ACM Trans. Archit. Code Optim. 9(4): 50:1-50:25 (2013) - [j23]Qixiao Liu, Miquel Moretó, Víctor Jiménez, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hardware support for accurate per-task energy metering in multicore systems. ACM Trans. Archit. Code Optim. 10(4): 34:1-34:27 (2013) - [j22]Alessandro Morari, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Trans. Computers 62(4): 813-826 (2013) - [j21]Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla:
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions. ACM Trans. Embed. Comput. Syst. 12(1s): 64:1-64:26 (2013) - [j20]Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu, Benoit Triquet, Guillem Bernat, Emery D. Berger, Jaume Abella, Franck Wartel, Michael Houston, Luca Santinelli, Leonidas Kosmidis, Code Lo, Dorin Maxim:
PROARTIS: Probabilistically Analyzable Real-Time Systems. ACM Trans. Embed. Comput. Syst. 12(2s): 94:1-94:26 (2013) - [j19]Marco Paolieri, Jörg Mische, Stefan Metzlaff, Mike Gerdes, Eduardo Quiñones, Sascha Uhrig, Theo Ungerer, Francisco J. Cazorla:
A hard real-time capable multi-core SMT processor. ACM Trans. Embed. Comput. Syst. 12(3): 79:1-79:26 (2013) - [j18]Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors. IEEE Trans. Parallel Distributed Syst. 24(12): 2513-2525 (2013) - [c60]Sylvain Girbal, Miquel Moretó, Arnaud Grasset, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Sami Yehia:
On the convergence of mainstream and mission-critical markets. DAC 2013: 185:1-185:10 - [c59]Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
A cache design for probabilistically analysable real-time systems. DATE 2013: 513-518 - [c58]Leonidas Kosmidis, Charlie Curtsinger, Eduardo Quiñones, Jaume Abella, Emery D. Berger, Francisco J. Cazorla:
Probabilistic timing analysis on conventional cache designs. DATE 2013: 603-606 - [c57]Theo Ungerer, Christian Bradatsch, Mike Gerdes, Florian Kluge, Ralf Jahr, Jörg Mische, João Fernandes, Pavel G. Zaykov, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Ian Broster, Nick Lay, David George, Eduardo Quiñones, Milos Panic, Jaume Abella, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka:
parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. DSD 2013: 363-370 - [c56]Mladen Slijepcevic, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
DTM: Degraded Test Mode for Fault-Aware Probabilistic Timing Analysis. ECRTS 2013: 237-248 - [c55]Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla:
Achieving timing composability with measurement-based probabilistic timing analysis. ISORC 2013: 1-8 - [c54]Milos Panic, Germán Rodríguez, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla:
On-chip ring network designs for hard-real time systems. RTNS 2013: 23-32 - [c53]Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Multi-level Unified Caches for Probabilistically Time Analysable Real-Time Systems. RTSS 2013: 360-371 - [c52]Javier Jalle, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
Deconstructing bus access control policies for Real-Time multicores. SIES 2013: 31-38 - [c51]Franck Wartel, Leonidas Kosmidis, Code Lo, Benoit Triquet, Eduardo Quiñones, Jaume Abella, Adriana Gogonel, Andrea Baldovin, Enrico Mezzetti, Liliana Cucu, Tullio Vardanega, Francisco J. Cazorla:
Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study. SIES 2013: 241-248 - [c50]Francisco J. Cazorla, Tullio Vardanega, Eduardo Quiñones, Jaume Abella:
Upper-bounding Program Execution Time with Extreme Value Theory. WCET 2013: 64-76 - [c49]Leonidas Kosmidis, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Applying Measurement-Based Probabilistic Timing Analysis to Buffer Resources. WCET 2013: 97-108 - 2012
- [j17]Petar Radojkovic, Sylvain Girbal, Arnaud Grasset, Eduardo Quiñones, Sami Yehia, Francisco J. Cazorla:
On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments. ACM Trans. Archit. Code Optim. 8(4): 34:1-34:25 (2012) - [j16]Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
CPU Accounting for Multicore Processors. IEEE Trans. Computers 61(2): 251-264 (2012) - [c48]Víctor Jiménez, Roberto Gioiosa, Francisco J. Cazorla, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell:
Making data prefetch smarter: adaptive prefetching on POWER7. PACT 2012: 137-146 - [c47]Petar Radojkovic, Vladimir Cakarevic, Miquel Moretó, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Optimal task assignment in multithreaded processors: a statistical approach. ASPLOS 2012: 235-248 - [c46]Liliana Cucu-Grosjean, Luca Santinelli, Michael Houston, Code Lo, Tullio Vardanega, Leonidas Kosmidis, Jaume Abella, Enrico Mezzetti, Eduardo Quiñones, Francisco J. Cazorla:
Measurement-Based Probabilistic Timing Analysis for Multi-path Programs. ECRTS 2012: 91-101 - [c45]Mikel Fernández, Roberto Gioiosa, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
Assessing the suitability of the NGMP multi-core processor in the space domain. EMSOFT 2012: 175-184 - [c44]Stelios Manousopoulos, Miquel Moretó, Roberto Gioiosa, Nectarios Koziris, Francisco J. Cazorla:
Characterizing thread placement in the IBM POWER7 processor. IISWC 2012: 120-130 - [c43]Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Alex Ramírez, Francisco J. Cazorla:
Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem. MICRO 2012: 401-412 - 2011
- [j15]Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Characterizing Power and Temperature Behavior of POWER6-Based System. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 228-241 (2011) - [j14]Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
Energy-Aware Accounting and Billing in Large-Scale Computing Facilities. IEEE Micro 31(3): 60-71 (2011) - [j13]Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems. SIGBED Rev. 8(3): 32-35 (2011) - [j12]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Dynamic Cache Partitioning Based on the MLP of Cache Misses. Trans. High Perform. Embed. Archit. Compil. 3: 3-23 (2011) - [c42]Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hybrid high-performance low-power and ultra-low energy reliable caches. Conf. Computing Frontiers 2011: 12 - [c41]Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero:
RVC: a mechanism for time-analyzable real-time processors with faulty caches. HiPEAC 2011: 97-106 - [c40]Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides:
RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 2011: 25-30 - [c39]Jaume Abella, Francisco J. Cazorla, Eduardo Quiñones, Arnaud Grasset, Sami Yehia, Philippe Bonnot, Dimitris Gizopoulos, Riccardo Mariani, Guillem Bernat:
Towards improved survivability in safety-critical systems. IOLTS 2011: 240-245 - [c38]Alessandro Morari, Roberto Gioiosa, Robert W. Wisniewski, Francisco J. Cazorla, Mateo Valero:
A Quantitative Analysis of OS Noise. IPDPS 2011: 852-863 - [c37]Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Julian Wolf, Theo Ungerer, Sascha Uhrig, Zlatko Petrov:
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks. ISORC 2011: 233-240 - [c36]Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Robert I. Davis, Mateo Valero:
IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2011: 280-290 - 2010
- [j11]Theo Ungerer, Francisco J. Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quiñones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Cassé, Sascha Uhrig, Irakli Guliashvili, Michael Houston, Florian Kluge, Stefan Metzlaff, Jörg Mische:
Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. IEEE Micro 30(5): 66-75 (2010) - [j10]Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero:
On the Problem of Evaluating the Performance of Multiprogrammed Workloads. IEEE Trans. Computers 59(12): 1722-1728 (2010) - [c35]Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Power and thermal characterization of POWER6 system. PACT 2010: 7-18 - [c34]Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero:
Load balancing using dynamic cache allocation. Conf. Computing Frontiers 2010: 153-164 - [c33]Kamil Kedzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
Power and performance aware reconfigurable cache for CMPs. IFMT 2010: 1:1-1:12 - [c32]Kamil Kedzierski, Miquel Moretó, Francisco J. Cazorla, Mateo Valero:
Adapting cache partitioning algorithms to pseudo-LRU replacement policies. IPDPS 2010: 1-12 - [c31]Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Thread to strand binding of parallel network applications in massive multi-threaded systems. PPoPP 2010: 191-202 - [c30]Víctor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
Trends and techniques for energy efficient architectures. VLSI-SoC 2010: 276-279 - [e1]Michael Beigl, Francisco Javier Cazorla-Almeida:
ARCS '10 - 23th International Conference on Architecture of Computing Systens 2010, Workshop Proceedings, February 22-23, 2010, Hannover, Germany. VDE Verlag 2010, ISBN 978-3-8007-3222-7 [contents]
2000 – 2009
- 2009
- [j9]Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
CPU Accounting in CMP Processors. IEEE Comput. Archit. Lett. 8(1): 17-20 (2009) - [j8]Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero:
An Analyzable Memory Controller for Hard Real-Time CMPs. IEEE Embed. Syst. Lett. 1(4): 86-90 (2009) - [j7]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero:
FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Oper. Syst. Rev. 43(2): 86-96 (2009) - [c29]Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. PACT 2009: 203-213 - [c28]Eduardo Quiñones, Emery D. Berger, Guillem Bernat, Francisco J. Cazorla:
Using Randomized Caches in Probabilistic Real-Time Systems. ECRTS 2009: 129-138 - [c27]Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero:
Hardware support for WCET analysis of hard real-time multicore systems. ISCA 2009: 57-68 - [c26]Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Characterizing the resource-sharing levels in the UltraSPARC T2 processor. MICRO 2009: 481-492 - [c25]Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Thread to Core Assignment in SMT On-Chip Multiprocessors. SBAC-PAD 2009: 67-74 - 2008
- [j6]Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith:
Multicore Resource Management. IEEE Micro 28(3): 6-16 (2008) - [c24]Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero:
Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation. ARCS 2008: 173-187 - [c23]Pedro Ángel Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luis Jiménez Laredo, Sally A. McKee:
Evolutionary system for prediction and optimization of hardware architecture performance. IEEE Congress on Evolutionary Computation 2008: 1941-1948 - [c22]Pedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luis Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee:
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks. EvoWorkshops 2008: 175-183 - [c21]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning. HiPEAC 2008: 337-352 - [c20]Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. ICPP 2008: 173-181 - [c19]Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero:
Balancing HPC applications through smart allocation of resources in MT processors. IPDPS 2008: 1-12 - [c18]Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero:
A Two-Level Load/Store Queue Based on Execution Locality. ISCA 2008: 25-36 - [c17]Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero:
Software-Controlled Priority Characterization of POWER5 Processor. ISCA 2008: 415-426 - [c16]Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero:
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD 2008: 63-70 - [c15]Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Measuring Operating System Overhead on CMT Processors. SBAC-PAD 2008: 133-140 - [c14]Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero:
A dynamic scheduler for balancing HPC applications. SC 2008: 41 - 2007
- [j5]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Explaining Dynamic Cache Partitioning Speed Ups. IEEE Comput. Archit. Lett. 6(1): 1-4 (2007) - [c13]Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Daniel A. Jiménez, Mateo Valero:
A Flexible Heterogeneous Multi-Core Architecture. PACT 2007: 13-24 - [c12]Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero:
FAME: FAirly MEasuring Multithreaded Architectures. PACT 2007: 305-316 - [c11]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning. PACT 2007: 418 - [c10]Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero:
On the Problem of Minimizing Workload Execution Time in SMT Processors. ICSAMOS 2007: 66-73 - [c9]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Online Prediction of Applications Cache Utility. ICSAMOS 2007: 169-177 - 2006
- [j4]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Predictable Performance in SMT Processors: Synergy between the OS and SMTs. IEEE Trans. Computers 55(7): 785-799 (2006) - 2005
- [j3]Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero:
Kilo-Instruction Processors: Overcoming the Memory Wall. IEEE Micro 25(3): 48-57 (2005) - [c8]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Architectural support for real-time task scheduling in SMT processors. CASES 2005: 166-176 - 2004
- [j2]Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
Optimising long-latency-load-aware fetch policies for SMT processors. Int. J. High Perform. Comput. Netw. 2(1): 45-54 (2004) - [j1]Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández:
QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24(4): 24-31 (2004) - [c7]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Predictable performance in SMT processors. Conf. Computing Frontiers 2004: 433-443 - [c6]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Implicit vs. Explicit Resource Allocation in SMT Processors. DSD 2004: 44-51 - [c5]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Feasibility of QoS for SMT. Euro-Par 2004: 535-540 - [c4]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Enabling SMT for real-time embedded systems. EUSIPCO 2004: 1341-1344 - [c3]Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. IPDPS 2004 - [c2]Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
Dynamically Controlled Resource Allocation in SMT Processors. MICRO 2004: 171-182 - 2003
- [c1]Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero:
Improving Memory Latency Aware Fetch Policies for SMT Processors. ISHPC 2003: 70-85
Coauthor Index
[j69] [c178] [c177] [c176] [c175] [c174] [j68] [j67] [j66] [j65] [j64] [j63] [j62] [j61] [c173] [c172] [c171] [c169] [c168] [c167] [c166] [c165] [i6] [i4] [i3] [j60] [c164] [c163] [c162] [c161] [j59] [j58] [j57] [j55] [j54] [c160] [c159] [c158] [c156] [c155] [i2] [i1] [j53] [j52] [c153] [c151] [c150] [c149] [c148] [c147] [c146] [c145] [c144] [j50] [j49] [j48] [j47] [j46] [c143] [c142] [c141] [c140] [c139] [c138] [c137] [c136] [c135] [c134] [c132] [c131] [c130] [c129] [c128] [c127] [j45] [j44] [j43] [j42] [j41] [c126] [c125] [c124] [c123] [c122] [c120] [c119] [c118] [j40] [j39] [j38] [j37] [j36] [c117] [c116] [c115] [c114] [c113] [c112] [c111] [c110] [c109] [c108] [c107] [c106] [c105] [j35] [j34] [j32] [j31] [c104] [c103] [c102] [c101] [c100] [c99] [c98] [c97] [c96] [c95] [c94] [c92] [c91] [c90] [c89] [c88] [j30] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [c79] [c77] [c76] [c75] [c74] [j29] [j28] [j27] [j26] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [j23] [j20] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c46] [j13] [c42] [c41] [c40] [c39]
Mikel Azkarate-askatsua
aka: Mikel Azkarate-askasua
aka: Mikel Azkarate-askasua
[j70] [c174] [j66] [j62] [c162] [j56] [i1] [j53] [j51] [c154] [c153] [c152] [c148] [c146] [c145] [c144] [j50] [c142] [c137] [c134] [c133] [c128] [j44] [j43] [c126] [c121] [c117] [c115] [c114] [j35] [c101] [c99] [c98] [c92] [c88] [c82] [j28] [j27] [c72] [c71] [c70] [c69] [c66] [j20] [c59] [c58] [c56] [c55] [c53] [c51] [c49] [c46]
[c178] [c177] [c176] [c174] [j67] [j64] [j62] [j61] [c173] [c172] [c171] [c168] [c165] [c164] [c163] [c158] [c156] [c155] [j52] [c151] [c149] [c148] [c145] [j50] [j46] [c143] [c139] [c134] [c130] [c129] [c127] [j45] [j44] [j41] [c126] [c124] [c120] [c117] [c116] [c110] [c109] [c106] [c101] [c89] [c88] [j30] [c82] [c76] [c74] [c51] [c46]
Jon Pérez 0001
aka: Jon Pérez-Cerrolaza
aka: Jon Pérez-Cerrolaza
[j38] [j37] [c114] [j35] [j32] [c103] [c102] [c101] [c100] [c99] [c98] [c95] [c92] [c90] [c88] [j30] [c86] [c85] [c84] [c83] [c82] [c81] [c79] [c77] [c75] [c74] [j28] [j27] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c63] [c62] [c61] [j21] [j20] [j19] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [j17] [c46] [c45] [j13] [c41] [c40] [c39] [c37] [c36] [j11] [j8] [c28] [c27]
[c153] [c108] [j34] [j33] [j31] [c78] [j29] [j26] [c64] [j24] [j23] [j22] [j18] [j16] [c47] [j15] [j14] [j13] [j12] [c42] [c41] [c40] [c38] [c36] [j10] [c35] [c34] [c33] [c32] [c31] [c30] [j9] [j8] [j7] [c29] [c27] [c26] [c25] [j6] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [j5] [c13] [c12] [c11] [c10] [c9] [j4] [j3] [c8] [j2] [j1] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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