BibTeX record conf/esscirc/Zhong0CSUM16

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@inproceedings{DBLP:conf/esscirc/Zhong0CSUM16,
  author    = {Jianyu Zhong and
               Yan Zhu and
               Chi{-}Hang Chan and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 12b 180MS/s 0.068mm\({}^{\mbox{2}}\) pipelined-SAR {ADC} with merged-residue
               {DAC} for noise reduction},
  booktitle = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
               Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
  pages     = {169--172},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ESSCIRC.2016.7598269},
  doi       = {10.1109/ESSCIRC.2016.7598269},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/conf/esscirc/Zhong0CSUM16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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