"A reduced jitter-sensitivity clock generation technique for ..."

Yang Jiang et al. (2010)

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DOI: 10.1109/APCCAS.2010.5774943

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-29

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Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. APCCAS 2010: 1011-1014

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