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ORCIDPaul J. Hurst
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- affiliation: University of California, Davis, USA
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2020 – today
- 2022
[j55]Christopher K. Su
, Paul J. Hurst, Stephen H. Lewis:
A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 620-633 (2022)- 2020
- [j54]Yi-Long Yu, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis:
A Two-Step ADC With Statistical Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2588-2601 (2020)
2010 – 2019
- 2019
- [j53]David J. Stoops, Jenny Kuo, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis:
Digital Background Calibration of a Split Current-Steering DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2854-2864 (2019) - 2018
- [c19]Natalie S. Killeen, Duy P. Nguyen, Alexander N. Stameroff, Anh-Vu Pham, Paul J. Hurst:
Design of a Wideband Bandpass Stacked HBT Distributed Amplifier in InP. ISCAS 2018: 1-5 - 2016
- [j52]Timothy A. Monk, Paul J. Hurst, Stephen H. Lewis:
Iterative Gain Enhancement in an Algorithmic ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(4): 459-469 (2016) - [c18]Mo M. Zhang, Paul J. Hurst, Stephen H. Lewis:
An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply. ISCAS 2016: 81-84 - 2015
- [j51]Dong Wang, John P. Keane, Paul J. Hurst, Stephen H. Lewis:
An Integrator-Based Pipelined ADC With Digital Calibration. IEEE Trans. Circuits Syst. II Express Briefs 62-II(9): 831-835 (2015) - 2014
- [j50]Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis:
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors. IEEE J. Solid State Circuits 49(6): 1397-1407 (2014) - 2013
- [j49]Omar A. Hafiz, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis:
Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling. IEEE J. Solid State Circuits 48(3): 749-759 (2013) - 2012
- [j48]Shankar Guhados, Paul J. Hurst, Stephen H. Lewis:
A Pipelined ADC With Metastability Error Rate <10-15 Errors/Sample. IEEE J. Solid State Circuits 47(9): 2119-2128 (2012) - [j47]Nattapol Sitthimahachaikul, Lakshmi P. Rao, Paul J. Hurst:
Canceling the ISI Due to Finite S/H Bandwidth in a Circular Buffer Forward Equalizer. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 188-192 (2012) - [j46]Nattapol Sitthimahachaikul, Lakshmi P. Rao, Paul J. Hurst:
Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(3): 652-663 (2012) - [j45]Lakshmi P. Rao, Nattapol Sitthimahachaikul, Paul J. Hurst:
Correcting the Effects of Mismatches in Time-Interleaved Analog Adaptive FIR Equalizers. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2529-2542 (2012) - [c17]Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis:
Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors. CICC 2012: 1-4 - 2011
- [j44]Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis:
A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR. IEEE J. Solid State Circuits 46(11): 2673-2684 (2011) - 2010
- [j43]Chi Ho Law, Paul J. Hurst, Stephen H. Lewis:
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors. IEEE J. Solid State Circuits 45(10): 2091-2103 (2010) - [c16]Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis:
A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR. ESSCIRC 2010: 422-425 - [c15]Mo M. Zhang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis:
Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver. ISCAS 2010: 4049-4052 - [c14]Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst:
A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs. ISCAS 2010: 4053-4056 - [c13]Oliver E. Gysel, Paul J. Hurst, Stephen H. Lewis:
Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks. SoCC 2010: 33-38
2000 – 2009
- 2009
- [j42]Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst:
A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters. IEEE J. Solid State Circuits 44(1): 240-246 (2009) - [j41]Haoyue Wang, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis:
Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA. IEEE J. Solid State Circuits 44(10): 2780-2789 (2009) - [j40]Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst:
Digital Calibration of a Nonlinear S/H. IEEE J. Sel. Top. Signal Process. 3(3): 454-471 (2009) - [j39]Tsung-Heng Tsai, Paul J. Hurst, Stephen H. Lewis:
Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 307-319 (2009) - [j38]Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst:
Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2075-2088 (2009) - [j37]Tunde Wang, Dong Wang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis:
A Level-Crossing Analog-to-Digital Converter With Triangular Dither. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2089-2099 (2009) - [j36]Mo M. Zhang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis:
Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver. IEEE Trans. Circuits Syst. II Express Briefs 56-II(10): 768-772 (2009) - [c12]Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst, Stephen H. Lewis:
An energy-aware multiple-input power supply with charge recovery for energy harvesting applications. ISSCC 2009: 298-299 - 2008
- [j35]Russell A. Hershbarger, Wenyan Jia, Kiam M. Tey, Kiyoshi Fukahori, Paul J. Hurst, Manprit Kapoor:
A Programmable Impedance Matching Circuit for Voiceband Modems. IEEE J. Solid State Circuits 43(2): 468-476 (2008) - [j34]Paul J. Hurst, Andy Norrell:
DAC Quantization-Noise Cancellation in an Echo-Canceling Transceiver. IEEE Trans. Circuits Syst. II Express Briefs 55-II(2): 111-115 (2008) - [c11]Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst:
A Full-Wave Rectifier for Interfacing with Multi-Phase Piezoelectric Energy Harvesters. ISSCC 2008: 302-303 - 2007
- [j33]Nathaniel J. Guilar, Frank Lau, Paul J. Hurst, Stephen H. Lewis:
A Passive Switched-Capacitor Finite-Impulse-Response Equalizer. IEEE J. Solid State Circuits 42(2): 400-409 (2007) - [c10]Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst:
Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter. ISCAS 2007: 1705-1708 - 2006
- [j32]John P. Keane, Paul J. Hurst, Stephen H. Lewis:
Digital background calibration for memory effects in pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(3): 511-525 (2006) - [j31]Tsung-Heng Tsai, Paul J. Hurst, Stephen H. Lewis:
Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1133-1137 (2006) - [c9]Mo M. Zhang, Paul J. Hurst:
Effect of nonlinearity in the CMFB circuit that uses the differential-difference amplifier. ISCAS 2006 - 2005
- [j30]Carl R. Grace, Paul J. Hurst, Stephen H. Lewis:
A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration. IEEE J. Solid State Circuits 40(5): 1038-1046 (2005) - [j29]John P. Keane, Paul J. Hurst, Stephen H. Lewis:
Background interstage gain calibration technique for pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(1): 32-43 (2005) - [j28]Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis:
Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter". IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(4): 822 (2005) - [c8]Nathaniel J. Guilar, Pak-Kim Lau, Paul J. Hurst, Stephen H. Lewis:
A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology. CICC 2005: 633-636 - [c7]Dong Wang, John P. Keane, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis:
Convergence analysis of a background interstage gain calibration technique for pipelined ADCs. ISCAS (4) 2005: 4058-4061 - 2004
- [j27]Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis:
A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration. IEEE J. Solid State Circuits 39(11): 1799-1808 (2004) - [j26]Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis:
Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 130-139 (2004) - [j25]Paul J. Hurst, Stephen H. Lewis, John P. Keane, Farbod Aram, Kenneth C. Dyer:
Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(2): 275-285 (2004) - [j24]Anthony Tong, Paul J. Hurst:
A mixed-signal approach for tuning continuous-time low-pass filters. IEEE Trans. Circuits Syst. II Express Briefs 51-II(6): 307-314 (2004) - [j23]Ryan Strong Prendergast, Bernard C. Levy, Paul J. Hurst:
Reconstruction of band-limited periodic nonuniformly sampled signals through multirate filter banks. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(8): 1612-1622 (2004) - 2003
- [j22]John P. Keane, Michael Q. Le, Paul J. Hurst:
Analog timing recovery for a noise-predictive decision-feedback equalizer. IEEE J. Solid State Circuits 38(2): 338-342 (2003) - [j21]Eric B. Blecker, Thomas M. McDonald, Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis:
Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue. IEEE J. Solid State Circuits 38(6): 1059-1062 (2003) - [c6]Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis:
A 12-bit 20-MS/s pipelined ADC with nested digital background calibration. CICC 2003: 409-412 - 2002
- [j20]Michael Q. Le, Paul J. Hurst, John P. Keane:
An adaptive analog noise-predictive decision-feedback equalizer. IEEE J. Solid State Circuits 37(2): 105-113 (2002) - [j19]Shafiq M. Jamal, Daihong Fu, Nick C.-J. Chang, Paul J. Hurst, Stephen H. Lewis:
A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration. IEEE J. Solid State Circuits 37(12): 1618-1627 (2002) - 2001
- [c5]Anthony Tong, Paul J. Hurst:
A mixed-signal tuning approach for continuous-time LPFs. ISCAS (1) 2001: 192-195 - 2000
- [j18]Pierte Roo, Richard R. Spencer, Paul J. Hurst:
A CMOS analog timing recovery circuit for PRML detectors. IEEE J. Solid State Circuits 35(1): 56-65 (2000) - [j17]Amit Gattani, David W. Cline, Paul J. Hurst, Paul M. Mosinskis:
A CMOS HDSL2 analog front-end. IEEE J. Solid State Circuits 35(12): 1964-1975 (2000)
1990 – 1999
- 1999
- [j16]Michael Q. Le, Paul J. Hurst, Kenneth C. Dyer:
An analog DFE for disk drives using a mixed-signal integrator. IEEE J. Solid State Circuits 34(5): 592-598 (1999) - [j15]Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis:
A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD. IEEE J. Solid State Circuits 34(12): 1812-1820 (1999) - 1998
- [j14]Daihong Fu, Kenneth C. Dyer, Stephen H. Lewis, Paul J. Hurst:
A digital background calibration technique for time-interleaved analog-to-digital converters. IEEE J. Solid State Circuits 33(12): 1904-1911 (1998) - [j13]Kenneth C. Dyer, Daihong Fu, Stephen H. Lewis, Paul J. Hurst:
An analog background calibration technique for time-interleaved analog-to-digital converters. IEEE J. Solid State Circuits 33(12): 1912-1919 (1998) - 1997
- [j12]Tanchu Shih, Lawrence Der, Stephen H. Lewis, Paul J. Hurst:
A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection. IEEE J. Solid State Circuits 32(2): 250-253 (1997) - [j11]Ravinder S. Kajley, Paul J. Hurst, James E. C. Brown:
A mixed-signal decision-feedback equalizer that uses a look-ahead architecture. IEEE J. Solid State Circuits 32(3): 450-459 (1997) - [j10]Bret C. Rothenberg, James E. C. Brown, Paul J. Hurst, Stephen H. Lewis:
A mixed-signal RAM decision-feedback equalizer for disk drives. IEEE J. Solid State Circuits 32(5): 713-721 (1997) - [j9]Chuc K. Thanh, Stephen H. Lewis, Paul J. Hurst:
A second-order double-sampled delta-sigma modulator using individual-level averaging. IEEE J. Solid State Circuits 32(8): 1269-1273 (1997) - 1996
- [j8]Ted Vinko Burmas, Kenneth C. Dyer, Paul J. Hurst, Stephen H. Lewis:
A second-order double-sampled delta-sigma modulator using additive-error switching. IEEE J. Solid State Circuits 31(3): 284-293 (1996) - [j7]James E. C. Brown, Paul J. Hurst, Lawrence Der:
A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-μm CMOS. IEEE J. Solid State Circuits 31(9): 1258-1266 (1996) - 1995
- [j6]Paul J. Hurst, Bret C. Rothenberg:
A programmable clock generator that uses noise shaping and its application in switched-capacitor filters. IEEE J. Solid State Circuits 30(4): 403-411 (1995) - [j5]Steven K. Berg, Paul J. Hurst, Stephen H. Lewis:
An 80-Msample/s video switched-capacitor filter using a parallel biquadratic structure. IEEE J. Solid State Circuits 30(8): 898-905 (1995) - [j4]Bret C. Rothenberg, Stephen H. Lewis, Paul J. Hurst:
A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure. IEEE J. Solid State Circuits 30(12): 1350-1356 (1995) - 1994
- [c4]James E. C. Brown, Paul J. Hurst, Lawrence Der, Iskender Agi:
A Comparison of Analog DFE Architectures for Disk-Drive Applications. ISCAS 1994: 99-102 - 1992
- [j3]Eric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi:
High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture. IEEE Trans. Circuits Syst. Video Technol. 2(4): 347-360 (1992) - [j2]Iskender Agi, Paul J. Hurst, Anil K. Jain:
A VLSI processor for parallel contour tracing. IEEE Trans. Signal Process. 40(2): 429-438 (1992) - 1990
- [j1]K. Wayne Current, Paul J. Hurst, Eric Shieh, Iskender Agi:
An evaluation of Radon transform computations using DSP chips. Mach. Vis. Appl. 3(2): 63-74 (1990) - [c3]Paul J. Hurst, K. Wayne Current, Iskender Agi, Eric Shieh:
A VLSI architecture for two-dimensional Radon transform computations. ICASSP 1990: 933-936
1980 – 1989
- 1989
- [c2]Stephen G. Azevedo, James M. Brase, Harry E. Martz, Anil K. Jain, K. Wayne Current, Paul J. Hurst:
A Radon transform computer for multidimensional signal processing. ICASSP 1989: 1457-1459 - 1988
- [c1]Iskender Agi, Paul J. Hurst, Anil K. Jain:
An expandable VLSI processor array approach to contour tracing. ICASSP 1988: 1969-1972
Coauthor Index
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