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ORCIDHiroo Masuda
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2010 – 2019
- 2010
[j21]Toshiki Kanamoto
, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto:
Impact of Self-Heating in Wire Interconnection on Timing. IEICE Trans. Electron. 93-C(3): 388-392 (2010)- [j20]Takashi Sato, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda:
A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(9): 1605-1611 (2010)
2000 – 2009
- 2009
- [j19]Hiroo Masuda, Takeshi Kida, Shin-ichi Ohkawa:
Comprehensive Matching Characterization of Analog CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 966-975 (2009) - [j18]Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato:
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 990-997 (2009) - [j17]Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto:
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3016-3023 (2009) - 2008
- [j16]Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda:
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis. IEICE Trans. Electron. 91-C(4): 647-654 (2008) - [j15]Shin-ichi Ohkawa, Hiroo Masuda, Yasuaki Inoue:
A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1062-1070 (2008) - 2006
- [j14]Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda:
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 847-855 (2006) - [j13]Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue:
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 856-864 (2006) - 2005
- [j12]Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda:
Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip. IEICE Trans. Electron. 88-C(5): 788-795 (2005) - [j11]Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda:
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(11): 3180-3187 (2005) - [j10]Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda:
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3453-3462 (2005) - [j9]Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3471-3478 (2005) - [c10]Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki:
Challenge: variability characterization and modeling for 65- to 90-nm processes. CICC 2005: 593-599 - [c9]Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki:
Approach for physical design in sub-100 nm era. ISCAS (6) 2005: 5934-5937 - [c8]Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ISQED 2005: 153-158 - [c7]Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED 2005: 586-591 - 2004
- [c6]Chieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda:
Large-scale linear circuit simulation with an inversed inductance matrix. ASP-DAC 2004: 511-516 - [c5]Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda:
DEPOGIT: dense power-ground interconnect architecture for physical design integrity. ASP-DAC 2004: 517-522 - [c4]Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda:
Efficient capacitance extraction method for interconnects with dummy fills. CICC 2004: 485-488 - 2003
- [j8]Atsushi Kurokawa, Kotaro Hachiya, Takashi Sato, Kazuya Tokumasu, Hiroo Masuda:
Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(4): 841-845 (2003) - [j7]Atsushi Kurokawa, Takashi Sato, Hiroo Masuda:
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2933-2941 (2003) - [j6]Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano:
Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology. IEEE J. Solid State Circuits 38(5): 702-708 (2003) - [c3]Atsushi Kurokawa, Takashi Sato, Hiroo Masuda:
Approximate formulae approach for efficient inductance extraction. ASP-DAC 2003: 143-148 - [c2]Takashi Sato, Hiroo Masuda:
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. ISQED 2003: 395-400
1990 – 1999
- 1998
- [c1]Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori:
TCAD/DA for MPU and ASIC Development. ASP-DAC 1998: 129-134 - 1991
- [j5]Hiroo Masuda, Jun'ichi Mano, Ryuichi Ikematsu, Hitoshi Sugihara, Yukio Aoki:
A submicrometer MOS transistor I-V model for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(2): 161-170 (1991)
1980 – 1989
- 1988
- [j4]Hiroo Masuda, Yukio Aoki, Jun'ichi Mano, Osamu Yamashiro:
MOSTSM: a physically based charge conservative MOSFET model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12): 1229-1236 (1988) - 1987
- [j3]Masanori Ohgo, Yasuko Takano, Akemi Moniwa, Shuichi Yamamoto, Yoshio Sakai, Hiroo Masuda, Hideo Sunami:
A Two-Dimensional Integrated Process Simulator: SPIRIT-I. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(3): 439-445 (1987) - [j2]Yukio Aoki, Hiroo Masuda, Shozo Shimada, Shoji Sato:
A New Design-Centering Methodology for VLSI Device Development. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(3): 452-461 (1987) - 1985
- [j1]Toru Toyabe, Hiroo Masuda, Yukio Aoki, Hiroko Shukuri, Takaaki Hagiwara:
Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(4): 482-488 (1985)
Coauthor Index
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