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"Crosstalk delay analysis of a 0.13-μm node test chip and precise ..."

Yasuhiko Sasaki et al. (2003)

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DOI: 10.1109/JSSC.2003.810062

access: closed

type: Journal Article

metadata version: 2022-04-20

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Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano:
Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology. IEEE J. Solid State Circuits 38(5): 702-708 (2003)

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