"A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry ..."

Hajime Kubosawa et al. (1999)

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DOI: 10.1109/4.799871

access: closed

type: Journal Article

metadata version: 2022-07-07

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Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada:
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. IEEE J. Solid State Circuits 34(11): 1619-1626 (1999)

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