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"A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip ..."

Kenji Kawai et al. (1999)

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DOI: 10.1109/4.736651

access: closed

type: Journal Article

metadata version: 2022-07-05

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Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino:
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. IEEE J. Solid State Circuits 34(1): 12-17 (1999)

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