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"A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive."

Daisaburo Takashima et al. (1999)

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DOI: 10.1109/4.799863

access: closed

type: Journal Article

metadata version: 2022-07-05

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  - https://dblp.org/rec/journals/jssc/TakashimaSKTOT99
Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka:
A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. IEEE J. Solid State Circuits 34(11): 1557-1563 (1999)

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