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ORCIDAlex R. Bugeja
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2000 – 2009
- 2006
[j5]Kush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan:
A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs. IEEE J. Solid State Circuits 41(8): 1856-1866 (2006)- 2005
- [c3]Kush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan:
A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACs. CICC 2005: 515-518 - 2004
- [j4]Gabriele Manganaro
, Sung-Ung Kwak, Alex R. Bugeja:
A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer. IEEE J. Solid State Circuits 39(11): 1829-1838 (2004) - 2003
- [c2]Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja:
A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer. CICC 2003: 429-432 - 2001
- [c1]Alex R. Bugeja, Sung-Ung Kwak:
Design of a 14 b 100 MS/s switched-capacitor pipelined ADC in RFSiGe BiCMOS. ISCAS (1) 2001: 428-431 - 2000
- [b1]Alex R. Bugeja:
High-Speed, High-Precision Digital-Analog Converters Designed for Spectral Performance. University of Illinois Urbana-Champaign, USA, 2000 - [j3]Alex R. Bugeja, Bang-Sup Song:
A self-trimming 14-b 100-MS/s CMOS DAC. IEEE J. Solid State Circuits 35(12): 1841-1852 (2000)
1990 – 1999
- 1999
- [j2]Alex R. Bugeja, Bang-Sup Song, Patrick L. Rakers, Steven F. Gillig:
A 14-b, 100-MS/s CMOS DAC designed for spectral performance. IEEE J. Solid State Circuits 34(12): 1719-1732 (1999) - 1997
- [j1]Alex R. Bugeja, W. Yang:
A reconfigurable VLSI coprocessing system for the block matching algorithm. IEEE Trans. Very Large Scale Integr. Syst. 5(3): 329-337 (1997)
Coauthor Index
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