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Hiroshi Nakayama
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2020 – today
- 2024
- [c7]Kentaro Katayama, Noboru Yoneoka, Kouichi Kanda, Hirotaka Tamura, Hiroshi Nakayama, Yasuhiro Watanabe:
Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs. ICCE 2024: 1-6
2010 – 2019
- 2016
- [c6]Kento Morita, Syoji Kobashi, Kaori Kashiwa, Hiroshi Nakayama, Shunichiro Kambara, Masakazu Morimoto, Shinichi Yoshiya, Satoru Aikawa:
Blumensaat's line detection for Quadrant method on MR images. FUZZ-IEEE 2016: 2144-2149 - [c5]Kento Morita, Manabu Nii, Shunichiro Kambara, Kaori Kashiwa, Hiroshi Nakayama, Shinichi Yoshiya, Syoji Kobashi:
Clinical big image data based pre-operative planning in ACL reconstruction. ICMLC 2016: 19-23 - 2015
- [c4]Kento Morita, Syoji Kobashi, Kaori Kashiwa, Hiroshi Nakayama, Shunichiro Kambara, Masakazu Morimoto, Shinichi Yoshiya, Satoru Aikawa:
Computer-aided Surgical Planning of Anterior Cruciate Ligament Reconstruction in MR Images. KES 2015: 1659-1667 - 2012
- [c3]Kentaro Kawakami, Yasuhiro Watanabe, Hiroshi Nakayama:
Adaptive spatial/temporal direct mode selection algorithm on H.264/AVC Encoder. ICCE 2012: 418-419 - 2010
- [j3]Masami Ishiguro, Hiroshi Nakayama, Yuki Shimauchi, Noriyuki Aibe, Ikuo Yoshihara, Moritoshi Yasunaga:
Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging. Artif. Life Robotics 15(3): 325-329 (2010) - [j2]Wen Ji, Makoto Hamaminato, Hiroshi Nakayama, Satoshi Goto:
Self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder. IEICE Electron. Express 7(17): 1283-1289 (2010) - [c2]Wen Ji, Makoto Hamaminato, Hiroshi Nakayama, Satoshi Goto:
A novel hardware-friendly self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder. EUSIPCO 2010: 1394-1398
2000 – 2009
- 2008
- [c1]Moritoshi Yasunaga, Yoshiki Yamaguchi, Hiroshi Nakayama, Ikuo Yoshihara, Naoki Koizumi, Jung Hwan Kim:
The Segmental-Transmission-Line: Its Design and Prototype Evaluation. ICES 2008: 130-140
1990 – 1999
- 1999
- [j1]Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada:
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. IEEE J. Solid State Circuits 34(11): 1619-1626 (1999)
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