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Joon-Wan Chai

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2000 – 2009

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2004
[j2]
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Changsik Yoo, Kye-Hyun Kyung, Kyunam Lim, Hi-Choon Lee, Joon-Wan Chai, Nak-Won Heo, Dong-Jin Lee, Chang-Hyun Kim:
A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. IEEE J. Solid State Circuits 39(6): 941-951 (2004)

1990 – 1999

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1999
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Changhyun Kim, Kye-Hyun Kyung, W.-P. Jeong, J.-S. Kim, Byung-Sik Moon, Joon-Wan Chai, S.-M. Yim, Jung-Hwan Choi, K.-H. Han, C.-J. Park, Hong-Sun Hwang, H. Choi, Sung-Burn Cho, Clemenz L. Portmann, Soo-In Cho:
A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. IEEE J. Solid State Circuits 34(5): 645-652 (1999)

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