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Hormoz Djahanshahi
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2020 – today
- 2022
- [j8]Omid Esmaeeli, Sam Lightbody, Amir Hossein Masnadi Shirazi, Hormoz Djahanshahi, Rod Zavari, Shahriar Mirabbasi, Sudip Shekhar:
A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20-28GHz LCVCO and a 51-62GHz Self-Mixing LCVCO. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6): 2351-2363 (2022) - 2020
- [c13]Amir Hossein Masnadi Shirazi, Mohammad Mahani, Hossein Miri Lavasani, Shahriar Mirabbasi, Sudip Shekhar, Rod Zavari, Hormoz Djahanshahi:
A Compact Dual-Core 26.1-to-29.9GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz. CICC 2020: 1-4
2010 – 2019
- 2018
- [c12]Zhichao Zhang, Li Chen, Hormoz Djahanshahi:
A Hardened-By-Design Technique for LC-Tank Voltage Controlled Oscillator. CCECE 2018: 1-4 - [c11]Zhichao Zhang, Li Chen, Hormoz Djahanshahi:
A SEE Insensitive CML Voltage Controlled Oscillator in 65nm CMOS. CCECE 2018: 1-4 - [c10]Milad Haghi Kashani, Reza Molavi, Hormoz Djahanshahi, Shahriar Mirabbasi:
On the Design of Vertical-Turn Solenoids for Magnetically Isolated Densely Integrated LC Oscillators. ISCAS 2018: 1-5 - 2016
- [j7]Amir Hossein Masnadi Shirazi, Amir Nikpaik, Reza Molavi, Sam Lightbody, Hormoz Djahanshahi, Mazhareddin Taghivand, Shahriar Mirabbasi, Sudip Shekhar:
On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise. IEEE J. Solid State Circuits 51(5): 1210-1222 (2016) - 2013
- [j6]Reza Molavi, Hormoz Djahanshahi, Rod Zavari, Shahriar Mirabbasi:
Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration. J. Electr. Comput. Eng. 2013: 364982:1-364982:8 (2013) - 2012
- [c9]Reza Molavi, Shahriar Mirabbasi, Hormoz Djahanshahi:
Design and verification of integrated inductors in CMOS. CCECE 2012: 1-4 - 2011
- [c8]Reza Molavi, Shahriar Mirabbasi, Hormoz Djahanshahi:
A 27-GHz low-power push-push LC VCO with wide tuning range in 65nm CMOS. ISCAS 2011: 1141-1144
2000 – 2009
- 2006
- [j5]Pedram Sameni, Chris Siu, Shahriar Mirabbasi, Hormoz Djahanshahi, Marwa Hamour, Krzysztof Iniewski, Jatinder Chana:
Modeling and Characterization of VCOs with MOS Varactors for RF Transceivers. EURASIP J. Wirel. Commun. Netw. 2006 (2006) - 2005
- [c7]Pedram Sameni, Chris Siu, Shahriar Mirabbasi, Hormoz Djahanshahi, Marwa Hamour, Krzysztof Iniewski, Jatinder Chana:
Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO. ISCAS (5) 2005: 5071-5074 - 2000
- [j4]Hormoz Djahanshahi, C. André T. Salama:
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications. IEEE J. Solid State Circuits 35(6): 847-855 (2000)
1990 – 1999
- 1999
- [j3]Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama:
Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS. IEEE J. Solid State Circuits 34(8): 1074-1083 (1999) - [c6]Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama:
Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling. CICC 1999: 601-604 - [c5]Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller:
Sensitivity study and improvements on a nonlinear resistive-type neuron circuit. ICECS 1999: 1029-1033 - [c4]Hormoz Djahanshahi, C. André T. Salama:
Differential 0.35µm CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications. ISCAS (2) 1999: 93-96 - 1998
- [j2]Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller:
A Low-Variation Nonlinear Neuron Circuit. J. Circuits Syst. Comput. 8(4): 447-451 (1998) - [j1]Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller:
Neural Network Integrated Circuits with Single-Block Mixed Signal Arrays. J. Circuits Syst. Comput. 8(5-6): 589-604 (1998) - [c3]Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama:
High-speed ECL-compatible serial I/O in 0.35 μm CMOS. ICECS 1998: 59-62 - 1996
- [c2]Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller:
Design and VLSI Implementation of a Unified Synapse-Neuron Architecture. Great Lakes Symposium on VLSI 1996: 228-233 - [c1]Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller:
A modular architecture for hybrid VLSI neural networks and its application in a smart photosensor. ICNN 1996: 868-873
Coauthor Index
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