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ORCIDToshio Shimada
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2000 – 2009
- 2008
[j8]Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada:
Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation. Inf. Media Technol. 3(4): 755-767 (2008)- [c16]Hideki Oshima, Ryotaro Kobayashi, Kazuki Shimura, Toshio Shimada:
Power consumption reduction scheme focusing on the Depth of Speculative Execution. CIT 2008: 207-212 - 2007
- [c15]Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada:
Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation. MEDEA@PACT 2007: 33-40 - 2006
- [j7]Akio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada:
Limits of Thread-Level Parallelism in Non-numerical Programs. Inf. Media Technol. 1(2): 851-859 (2006) - 2003
- [c14]Hajime Shimada, Hideki Ando, Toshio Shimada:
Pipeline stage unification: a low-energy consumption technique for future mobile processors. ISLPED 2003: 326-329 - 2002
- [c13]Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada:
A preactivating mechanism for a VT-CMOS cache using address prediction. ISLPED 2002: 247-250
1990 – 1999
- 1999
- [j6]Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada:
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. IEEE J. Solid State Circuits 34(11): 1619-1626 (1999) - [c12]Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata:
An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. EUROMICRO 1999: 1432-1440 - 1993
- [c11]Kei Hiraki, Toshio Shimada, Satoshi Sekiguchi:
Empirical Study of Latency Hiding on a Fine-Grain Parallel Processor. International Conference on Supercomputing 1993: 220-229 - [c10]Kenji Nishida, Kenji Toda, Toshio Shimada, Yoshinori Yamaguchi:
The Hardware Architecture of the CODA Real-Time Parallel Processor. PARCO 1993: 395-402 - 1992
- [j5]Toshio Shimada, Kenji Toda, Kenji Nishida:
Real-Time Parallel Architecture for Sensor Funsion. J. Parallel Distributed Comput. 15(2): 143-152 (1992) - [c9]Kenji Toda, Kenji Nishida, Shuichi Sakai
, Toshio Shimada:
A priority forwarding scheme for real-time multistage interconnection networks. RTSS 1992: 208-217 - 1991
- [c8]Satoshi Sekiguchi, Toshio Shimada, Kei Hiraki:
Sequential description and parallel execution language DFCII dataflow supercomputers. ICS 1991: 57-66 - [c7]Kenji Toda, Kenji Nishida, Yoshinobu Uchibori, Shuichi Sakai, Toshio Shimada:
Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism. IPPS 1991: 336-343 - 1990
- [c6]Toshitsugu Yuba, Toshio Shimada, Yoshinori Yamaguchi, Kei Hiraki, Shuichi Sakai:
Dataflow computer development in Japan. ICS 1990: 140-147
1980 – 1989
- 1989
- [j4]Toshio Shimada, Satoshi Sekiguchi, Kei Hiraki:
Data flow language DFC: Design and implementation. Syst. Comput. Jpn. 20(6): 1-10 (1989) - 1988
- [c5]Kei Hiraki, Satoshi Sekiguchi, Toshio Shimada:
Efficient vector processing on dataflow supercomputer SIGMA-1. SC 1988: 374-381 - 1987
- [j3]Kei Hiraki, Satoshi Sekiguchi, Toshio Shimada:
Load scheduling schemes using inter - PE network. Syst. Comput. Jpn. 18(1): 55-66 (1987) - [c4]Toshitsugu Yuba, Kei Hiraki, Toshio Shimada, Satoshi Sekiguchi, Kenji Nishida:
The SIGMA-1 dataflow computer. FJCC 1987: 578-585 - 1986
- [c3]Kei Hiraki, Kenji Nishida, Satoshi Sekiguchi, Toshio Shimada:
Maintenance Architecture and Its LSI Implementation of a Dataflow Computer with a Large Number of Processors. ICPP 1986: 584-591 - [c2]Toshio Shimada, Kei Hiraki, Kenji Nishida, Satoshi Sekiguchi:
Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations. ISCA 1986: 226-234 - 1984
- [j2]Kei Hiraki, Kenji Nishida, Toshio Shimada:
Evaluation of Associative Memory Using Parallel Chained Hashing. IEEE Trans. Computers 33(9): 851-855 (1984) - [c1]Toshio Shimada, Kei Hiraki, Kenji Nishida:
An Architecture of a Data Flow Machine and Its Evaluation. COMPCON 1984: 486-490 - 1983
- [j1]Toshitsugu Yuba, Yoshinori Yamaguchi, Toshio Shimada:
A Control Mechanism of a Lisp-Based Data-Driven Machine. Inf. Process. Lett. 16(3): 139-143 (1983)
Coauthor Index
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