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ORCIDHerman Schmit
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- affiliation: Carnegie Mellon University, Pittsburgh, USA
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2020 – today
- 2023
[c49]Alessandro Tempia Calvino, Alan Mishchenko, Herman Schmit, Ethan Mahintorabi, Giovanni De Micheli, Xiaoqing Xu:
Improving Standard-Cell Design Flow using Factored Form Optimization. DAC 2023: 1-6- 2022
- [c48]Herman Schmit, Matthew Denton:
Multi-input Serial Adders for FPGA-like Computational Fabric. FPGA 2022: 35-41 - [c47]Matthew Denton, Herman Schmit:
Direct Spatial Implementation of Sparse Matrix Multipliers for Reservoir Computing. HPCA 2022: 1-11 - 2021
- [i1]Matthew Denton, Herman Schmit:
Direct Spatial Implementation of Sparse Matrix Multipliers for Reservoir Computing. CoRR abs/2101.08884 (2021)
2010 – 2019
- 2019
- [j7]David M. Lewis
, Herman Schmit:
Spatial Timing Analysis With Exact Propagation of Delay and Application to FPGA Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2153-2166 (2019) - 2017
- [c46]David Greenhill, Ron Ho, David M. Lewis, Herman Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, Dana How, Peter McElheny, Keith Duwel, Jeffrey Schulz, Darren Faulkner, Gopal Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay:
3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration. ISSCC 2017: 54-55 - 2016
- [c45]Carl Ebeling, Dana How, David M. Lewis, Herman Schmit:
Stratix™ 10 High Performance Routable Clock Networks. FPGA 2016: 64-73 - [c44]Herman Schmit, Randy Huang:
Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper. ISLPED 2016: 152-153
2000 – 2009
- 2008
- [c43]Herman Schmit, Amit Gupta, Radu Ciobanu:
Placement challenges for structured ASICs. ISPD 2008: 84-86 - 2005
- [j6]Herman Schmit, Vikas Chandra:
Layout techniques for FPGA switch blocks. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 96-105 (2005) - [e2]Herman Schmit, Steven J. E. Wilton:
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005. ACM 2005, ISBN 1-59593-029-9 [contents] - 2004
- [c42]R. Reed Taylor, Herman Schmit:
Enabling energy efficiency in via-patterned gate array devices. DAC 2004: 874-878 - [c41]Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi:
An Interconnect Channel Design Methodology for High Performance Integrated Circuits. DATE 2004: 1138-1143 - [c40]Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi:
A power aware system level interconnect design methodology for latency-insensitive systems. ICCAD 2004: 275-282 - [c39]R. Reed Taylor, Herman Schmit:
Creating a power-aware structured ASIC. ISLPED 2004: 74-77 - [c38]Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit:
Evaluating Alternative Implementations for LDPC Decoder Check Node Function. ISVLSI 2004: 77-82 - [c37]Vikas Chandra, Anthony Xu, Herman Schmit:
A low power approach to system level pipelined interconnect design. SLIP 2004: 45-52 - [e1]Russell Tessier, Herman Schmit:
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004. ACM 2004, ISBN 1-58113-829-6 [contents] - 2003
- [c36]Kim Yaw Tong, V. Kheterpal, Vyacheslav Rovner, Lawrence T. Pileggi, Herman Schmit:
Regular logic fabrics for a via patterned gate array (VPGA). CICC 2003: 53-56 - [c35]Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, Kim Yaw Tong:
Exploring regular fabrics to optimize the performance-cost trade-off. DAC 2003: 782-787 - [c34]Aneesh Koorapaty, Vikas Chandra, Kim Yaw Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit:
Heterogeneous Programmable Logic Block Architectures. DATE 2003: 11118-11119 - [c33]Benjamin A. Levine, Herman Schmit:
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable. FCCM 2003: 101-110 - [c32]Hiroto Kagotani, Herman Schmit:
Asynchronous PipeRench: Architecture and Performance Estimations. FCCM 2003: 121- - [c31]Herman Schmit:
Extra-dimensional Island-Style FPGAs. FPL 2003: 406-415 - [c30]Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit:
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. FPL 2003: 426-436 - [c29]Matthew Moe, Herman Schmit:
Floorplanning of pipelined array modules using sequence pairs. ISPD 2003: 143-150 - [c28]Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi:
An architectural exploration of via patterned gate arrays. ISPD 2003: 184-189 - [c27]Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis:
The Sandbox Design Experience Course. MSE 2003: 39-40 - [c26]Thomas Kroll, Herman Schmit, Dave Landis:
CAD Tool Support For A Multi-University Soc Certificate Program: The Digital Sandbox. MSE 2003: 47-48 - 2002
- [c25]Herman Schmit, David Whelihan, Andrew Tsai, Matthew Moe, Benjamin A. Levine, R. Reed Taylor:
PipeRench: A virtualized programmable datapath in 0.18 micron technology. CICC 2002: 63-66 - [c24]David Whelihan, Herman Schmit:
Memory optimization in single chip network switch fabrics. DAC 2002: 530-535 - [c23]Herman Schmit, Benjamin A. Levine, Benjamin Ylvisaker:
Queue Machines: Hardware Compilation in Hardware. FCCM 2002: 152- - [c22]Herman Schmit, Vikas Chandra:
FPGA switch block layout and evaluation. FPGA 2002: 11-18 - [c21]Silviu M. S. A. Chiricescu, Michael A. Schuette, Robin Glinton, Herman Schmit:
Morphable Multipliers. FPL 2002: 647-656 - [c20]Vikas Chandra, Herman Schmit:
Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach. ISVLSI 2002: 35-40 - [c19]Silviu M. S. A. Chiricescu, Michael A. Schuette, Herman Schmit, Robin Glinton:
Synthesis of Morphable Multipliers. IWLS 2002: 109-113 - 2001
- [c18]Pradeep K. Khosla, Herman Schmit, Mary Jane Irwin, Narayanan Vijaykrishnan, Tom Cain, Steven P. Levitan, Dave Landis:
SoC Design Skills: Collaboration Builds a Stronger SoC Design Team. MSE 2001: 42-43 - 2000
- [j5]Seth Copen Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matthew Moe, R. Reed Taylor:
PipeRench: A Reconfigurable Architecture and Compiler. Computer 33(4): 70-77 (2000) - [j4]Herman Schmit, Srihari Cadambi, Matthew Moe, Seth Copen Goldstein:
Pipeline Reconfigurable FPGAs. J. VLSI Signal Process. 24(2-3): 129-146 (2000) - [c17]Benjamin A. Levine, R. Reed Taylor, Herman Schmit:
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware. FCCM 2000: 217-226 - [c16]Herman Schmit, Ray Andraka, Philip Friedin, Satnam Singh, Tim Southgate:
The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers. FPGA 2000: 101 - [c15]Herman Schmit, David Whelihan, Peter Kamarchik, Frank Gennari:
Scalable interconnect and power distribution for island-style FPGAs (poster abstract). FPGA 2000: 221 - [c14]Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen:
PipeRench implementation of the instruction path coprocessor. MICRO 2000: 147-158
1990 – 1999
- 1999
- [c13]Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass:
Vertical Benchmarks for CAD. DAC 1999: 408-413 - [c12]Ronald Laufer, R. Reed Taylor, Herman Schmit:
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing. FCCM 1999: 200-208 - [c11]Herman Schmit:
Extra-Dimensional Island-Style FPGAs. FPGA 1999: 247 - [c10]Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, Ronald Laufer:
PipeRench: A Coprocessor for Streaming multimedia Acceleration. ISCA 1999: 28-39 - [c9]Bharath Ramasubramanian, Herman Schmit, L. Richard Carley:
Mixed-swing quadrail for low power dual-rail domino logic. ISLPED 1999: 82-84 - 1998
- [j3]Herman Schmit, Donald E. Thomas:
Address generation for memories containing multiple arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5): 377-385 (1998) - [c8]Ram Krishnamurthy, Herman Schmit, L. Richard Carley:
A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques. CICC 1998: 499-502 - [c7]Matthew Moe, Herman Schmit, Seth Copen Goldstein:
Characterization and Parameterization of a Pipeline Reconfigurable FPGA. FCCM 1998: 294-295 - [c6]Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas:
Managing Pipeline-Reconfigurable FPGAs. FPGA 1998: 55-64 - 1997
- [j2]Herman Schmit, Donald E. Thomas:
Synthesis of application-specific memory designs. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 101-111 (1997) - [c5]Herman Schmit:
Incremental reconfiguration for pipelined applications. FCCM 1997: 47-55 - [c4]Herman Schmit:
Is Reconfigurable Computing Commercially Viable (panel)? FPGA 1997: 101 - 1995
- [c3]Herman Schmit, Donald E. Thomas:
Hidden Markov modeling and fuzzy controllers in FPGAs. FCCM 1995: 214-221 - [c2]Herman Schmit, Donald E. Thomas:
Address generation for memories containing multiple arrays. ICCAD 1995: 510-514 - [c1]Herman Schmit, Donald E. Thomas:
Array mapping in behavioral synthesis. ISSS 1995: 90-95 - 1993
- [j1]Donald E. Thomas, Jay K. Adams, Herman Schmit:
A Model and Methodology for Hardware-Software Codesign. IEEE Des. Test Comput. 10(3): 6-15 (1993)
Coauthor Index
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