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"28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS ..."

Kentaro Yoshioka et al. (2017)

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DOI: 10.1109/ISSCC.2017.7870469

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-07

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  - conf/isscc/YoshiokaSWKKIFS17
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  - https://dblp.org/rec/conf/isscc/YoshiokaSWKKIFS17
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura:
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. ISSCC 2017: 478-479

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