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"23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache."

Tah-Kang Joseph Ting et al. (2017)

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DOI: 10.1109/ISSCC.2017.7870432

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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  dblp key:
  - conf/isscc/TingWWWWLTYHLHH17
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  - https://dblp.org/rec/conf/isscc/TingWWWWLTYHLHH17
Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu:
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. ISSCC 2017: 404-405

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