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Seong-Young Seo
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2010 – 2019
- 2017
- [j3]Kyomin Sohn
, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Hyunui Lee, Seok-Yong Kang, Young-Soo Sohn, Jung-Hwan Choi, Yong-Cheol Bae, Seong-Jin Jang, Gyo-Young Jin:
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution. IEEE J. Solid State Circuits 52(1): 250-260 (2017) - 2016
- [c4]Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jaewook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin:
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. ISSCC 2016: 316-317 - 2013
- [j2]Seong-Young Seo, Jung-Hoon Chun, Young-Hyun Jun, Kee-Won Kwon:
An all-digital PLL with supply insensitive digitally controlled oscillator. IEICE Electron. Express 10(5): 20120902 (2013) - 2011
- [j1]Seong-Young Seo, Jung-Hoon Chun, Young-Hyun Jun, Seok Kim, Kee-Won Kwon:
A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 632-636 (2011) - 2010
- [c3]Seong-Young Seo, Suk Chan Kim, Young Il Kim:
MS aided MBS enhancement algorithm. ICTC 2010: 101-102 - [c2]Young-Il Kim, Gonchigsumlaa Khishigjargal, Soon Young Song, Yong Su Lee, Park Dae Geun, Chun Sun Sim, Park Young Soo, Yeonjoon Chung, Cheol-Hye Cho, Won Ryu, Seong-Young Seo, Suk Chan Kim, Naimannaran Chuluunbandi:
3D image transmission technology for mobile IPTV. ICTC 2010: 280-283
2000 – 2009
- 2009
- [c1]Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim:
1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. ISSCC 2009: 128-129
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