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"Jitter-reduction and pulse-width-distortion compensation circuits for a ..."

Jun Terada et al. (2009)

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DOI: 10.1109/ISSCC.2009.4977329

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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  - conf/isscc/TeradaONKKY09
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Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto:
Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. ISSCC 2009: 104-105

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