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ORCID12th FCCM 2004: Napa, CA, USA
- 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings. IEEE Computer Society 2004, ISBN 0-7695-2230-0
Architecture
- Philip James-Roxby, Gordon J. Brebner
, Dennis Bemmann:
Time-Critical Software Deceleration in an FCCM. 3-12 - André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton:
Design Patterns for Reconfigurable Computing. 13-23 - Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. 24-33
Tools I
- David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee:
Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. 37-46 - Jingzhao Ou, Viktor K. Prasanna:
PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs. 47-56
Arithmetic I
- Mark L. Chang, Scott Hauck:
Automated Least-Significant Bit Datapath Optimization for FPGAs. 59-67 - Kuen Hung Tsoi, Chun Hok Ho, Jackson H. C. Yeung, Philip Heng Wai Leong:
An Arithmetic Library and Its Application to the N-body Problem. 68-78 - Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung:
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. 79-88
Communications Applications
- Jian Liang, Russell Tessier, Dennis Goeckel:
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. 91-100 - Dong-U Lee, Wayne Luk, Connie Wang, Christopher R. Jones, Michael Smith, John D. Villasenor:
A Flexible Hardware Encoder for Low-Density Parity-Check Codes. 101-111
Networking I
- Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West:
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers. 115-124 - Young H. Cho, William H. Mangione-Smith:
Deep Packet Filter with Dedicated Logic and Read Only Memories. 125-134 - Zachary K. Baker, Viktor K. Prasanna:
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs. 135-144
Applications I
- Miriam Leeser, Shawn Miller, Haiqian Yu:
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications. 147-155 - James P. Durbano, Fernando E. Ortiz, John R. Humphrey, Petersen F. Curt, Dennis W. Prather:
FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method. 156-163
Tools II
- Hassan Al Atat, Iyad Ouaiss:
Register Binding for FPGAs with Embedded Memory. 167-175 - Mehdi Baradaran Tahoori, Subhasish Mitra:
Defect and Fault Tolerance of Reconfigurable Molecular Computing. 176-185 - Maya B. Gokhale, Christine Ahrens, Janette Frigo, Christophe Wolinski:
Communications Scheduling for Concurrent Processes on Reconfigurable Computers. 186-193
Applications II
- Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow:
Reconfigurable Molecular Dynamics Simulator. 197-206 - He Chuan, Mi Lu, Chuanwen Sun:
Accelerating Seismic Migration Using FPGA-Based Coprocessor Platform. 207-216
Arithmetic II
- Keith D. Underwood, K. Scott Hemmert:
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance. 219-228 - Christopher C. Doss, Robert L. Riley Jr.:
FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit. 229-238 - Steven D. Krueger, Peter-Michael Seidel:
Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs. 239-246
Networking II
- Christopher R. Clark, David E. Schimmel:
Scalable Pattern Matching for High Speed Networks. 249-257 - Ioannis Sourdis, Dionisios N. Pnevmatikatos:
Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching. 258-267
Posters
- N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured System Methodology for FPGA Based System-on-A-Chip Design. 271-272 - Emre Özer, Andy Nisbet, David Gregg:
Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs. 273-274 - Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. 275-276 - Gregory V. Larchev, Jason D. Lohn:
Hardware-in-the-Loop Evolution of a 3-bit Multiplier. 277-278 - Ciaran McIvor, Máire McLoone, John V. McCanny:
FPGA Montgomery Multiplier Architectures - A Comparison. 279-282 - Sebastian Wallner:
Design Methodology of a Configurable System-on-Chip Architecture. 283-284 - George A. Constantinides, Abunaser Miah, Nalin Sidahao:
Word-Length Optimization of Folded Polynomial Evaluation. 285-286 - Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung:
Migrating Functionality from ROMS to Embedded Multipliers. 287-288 - David Wentzlaff, Anant Agarwal:
A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation. 289-290 - Valeri F. Tomashau, Tom Kean:
Validation of an Advanced Encryption Standard (AES) IP Core. 291-292 - Sami Khawam, Tughrul Arslan, Fred Westall:
Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays. 293-295 - Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis:
The MOLEN Processor Prototype. 296-299 - Tom Van Court, Yongfeng Gu, Martin C. Herbordt:
FPGA Acceleration of Rigid Molecule Interactions. 300-301 - Philip James-Roxby, Paul R. Schumacher, Charlie Ross:
A Single Program Multiple Data Parallel Processing Platform for FPGAs. 302-303 - Sebastian Lange, Martin Middendorf:
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration. 304-305 - Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz:
A Generator of High-Speed Floating-Point Modules. 306-307 - Alireza Hodjat, Ingrid Verbauwhede:
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA. 308-309 - Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak:
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding. 310-311 - Dirk Eilers, Helmut Steckenbiller, Andreas Herkersdorf:
Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems. 312-315 - Long Bu, John A. Chandy:
FPGA Based Network Intrusion Detection using Content Addressable Memories. 316-317 - Charlie Ross, A. P. Wim Böhm:
Using FIFOs in Hardware-Software Co-Design for FPGA Based Embedded Systems. 318-319 - Jianchun Li, Christos A. Papachristou, Raj Shekhar:
A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing. 320-321 - Michael Attig, Sarang Dharmapurikar, John W. Lockwood:
Implementation Results of Bloom Filters for String Matching. 322-323 - Daniel J. Allred, Walter Huang, Venkatesh Krishnan, Heejong Yoo, David V. Anderson:
An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic. 324-325 - Rajarshi Mukherjee, Seda Ogrenci Memik:
Power Management for FPGAs: Power-Driven Design Partitioning. 326-327 - Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. 328-329 - Deepak Boppana, Kully Dhanoa, Jesse Kempa:
FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm. 330-331 - Andrea Cappelli, Andrea Lodi, Claudio Mucci, Mario Toma, Fabio Campi:
A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow. 332-333 - Haoyu Song, Jing Lu, John W. Lockwood, James Moscola:
Secure Remote Control of Field-programmable Network Devices. 334-335 - Neil Steiner, Peter M. Athanas:
An Alternate Wire Database for Xilinx FPGAs. 336-337 - Sumit Mohanty, Viktor K. Prasanna:
Duty Cycle Aware Application Design using FPGAs. 338-339 - Shawn Phillips, Akshay Sharma, Scott Hauck:
Automating the Layout of Reconfigurable Subsystems Via Template Reduction. 340-341 - Matthias Dyer, Marco Platzner, Lothar Thiele:
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. 342-344
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