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Sudarshan Banerjee
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2010 – 2019
- 2010
- [j7]Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
:
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. ACM Trans. Reconfigurable Technol. Syst. 3(3): 18:1-18:30 (2010)
2000 – 2009
- 2009
- [j6]John Augustine, Sudarshan Banerjee, Sandy Irani:
Strip packing with precedence constraints and strip packing with release times. Theor. Comput. Sci. 410(38-40): 3792-3803 (2009) - [j5]Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
:
Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 234-247 (2009) - 2008
- [j4]Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt
, Nalini Venkatasubramanian:
Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies. ACM Trans. Embed. Comput. Syst. 7(2): 9:1-9:19 (2008) - 2007
- [c12]Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
, Juanjo Noguera:
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. DAC 2007: 771-776 - [c11]Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee:
Energy-aware co-processor selection for embedded processors on FPGAs. ICCD 2007: 158-163 - [i1]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. CoRR abs/0710.4820 (2007) - 2006
- [j3]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt
, Laura Pozzi, Paolo Ienne:
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 754-762 (2006) - [j2]Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
:
Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1189-1202 (2006) - [c10]Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
:
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. ASP-DAC 2006: 491-496 - [c9]Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt
, Nalini Venkatasubramanian:
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. CODES+ISSS 2006: 16-21 - [c8]Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
:
Minimizing peak power for application chains on architectures with partial dynamic reconfiguration. FPT 2006: 273-276 - [c7]John Augustine, Sudarshan Banerjee, Sandy Irani:
Strip packing with precedence constraints and strip packing with release times. SPAA 2006: 180-189 - [c6]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt
, Paolo Ienne, Laura Pozzi:
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design 2006: 651-656 - 2005
- [c5]Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
:
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. DAC 2005: 335-340 - [c4]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt
, Laura Pozzi, Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE 2005: 1246-1251 - [c3]Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
:
Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. FCCM 2005: 273-274 - 2004
- [c2]Sudarshan Banerjee, Nikil D. Dutt
:
Efficient search space exploration for HW-SW partitioning. CODES+ISSS 2004: 122-127 - [c1]Sudarshan Banerjee, Nikil D. Dutt
:
FIFO power optimization for on-chip networks. ACM Great Lakes Symposium on VLSI 2004: 187-191
1990 – 1999
- 1997
- [j1]Sudarshan Banerjee, Sanjeev Saxena:
Parallel Algorithms for Finding the Most Vital Edge in Weighted Graphs. J. Parallel Distributed Comput. 46(1): 101-104 (1997)
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