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ORCIDFrank Hannig
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- affiliation: University of Erlangen-Nuremberg, Germany
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2020 – today
- 2023
[c136]Muhammad Sabih
, Mikail Yayla, Frank Hannig, Jürgen Teich, Jian-Jia Chen:
Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. EuroMLSys@EuroSys 2023: 87-93- [i15]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR abs/2306.12742 (2023) - 2022
- [j39]Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende:
The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurr. Comput. Pract. Exp. 34(14) (2022) - [j38]Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich:
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2661-2666 (2022) - [j37]Frank Hannig, Steven Derrien:
Special Issue on Applied Reconfigurable Computing. J. Signal Process. Syst. 94(9): 847-848 (2022) - [c135]Muhammad Sabih, Frank Hannig, Jürgen Teich:
DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. EuroMLSys@EuroSys 2022: 109-115 - [c134]Patrick Plagwitz, Frank Hannig, Jürgen Teich:
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. FPL 2022: 17-23 - [c133]Muhammad Sabih, Ashutosh Mishra, Frank Hannig, Jürgen Teich:
MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. IGSC 2022: 1-8 - [c132]Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich:
Hardware-Aware Evolutionary Filter Pruning. SAMOS 2022: 283-299 - 2021
- [j36]Frank Hannig, Jürgen Teich:
Open Source Hardware. Computer 54(10): 111-115 (2021) - [j35]Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33(14) (2021) - [j34]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. 18(3): 765-777 (2021) - [j33]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. 20(5): 49:1-49:31 (2021) - [j32]Frank Hannig, Dirk Koch:
Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. J. Signal Process. Syst. 93(12): 1363-1364 (2021) - [c131]Muhammad Sabih, Frank Hannig, Jürgen Teich:
Fault-Tolerant Low-Precision DNNs using Explainable AI. DSN Workshops 2021: 166-174 - [c130]Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich:
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. FCCM 2021: 10-19 - [c129]Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich:
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. FPL 2021: 388 - [c128]Bo Qiao, Jürgen Teich, Frank Hannig:
An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. IPDPS Workshops 2021: 387-396 - [c127]Stefan Groth, Jürgen Teich, Frank Hannig:
Efficient Application of Tensor Core Units for Convolving Images. SCOPES 2021: 1-6 - [e5]Steven Derrien, Frank Hannig, Pedro C. Diniz, Daniel Chillet:
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings. Lecture Notes in Computer Science 12700, Springer 2021, ISBN 978-3-030-79024-0 [contents] - [i14]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR abs/2101.04395 (2021) - [i13]Frank Hannig, Paolo Meloni, Matteo Spallanzani, Matthias Ziegler:
Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021). CoRR abs/2102.00818 (2021) - 2020
- [j31]Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, Jürgen Teich:
A bibliometric approach for detecting the gender gap in computer science. Commun. ACM 63(5): 74-80 (2020) - [j30]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig:
AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3202-3214 (2020) - [c126]Dirk Koch, Frank Hannig, Javier Navaridas:
Message from the Conference Chairs - ASAP 2020. ASAP 2020: i-ii - [c125]Stefan Groth, Daniel Grünewald, Jürgen Teich, Frank Hannig:
A runtime system for finite element methods in a partitioned global address space. CF 2020: 39-48 - [c124]Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig:
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC 2020: 1-6 - [c123]Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende:
HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. Euro-Par Workshops 2020: 185-196 - [c122]Bo Qiao, Oliver Reiche, Jürgen Teich, Frank Hannig:
Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. GPGPU@PPoPP 2020: 11-20 - [c121]Christian Heidorn, Frank Hannig, Jürgen Teich:
Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. SCOPES 2020: 26-31 - [c120]Bo Qiao, Oliver Reiche, M. Akif Özkan, Jürgen Teich, Frank Hannig:
Efficient parallel reduction on GPUs with Hipacc. SCOPES 2020: 58-61 - [c119]Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich:
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT 2020: 1-6 - [p6]Christian Lengauer, Sven Apel, Matthias Bolten, Shigeru Chiba, Ulrich Rüde, Jürgen Teich, Armin Größlinger, Frank Hannig, Harald Köstler, Lisa Claus, Alexander Grebhahn, Stefan Groth, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt, Jonas Schmitt:
ExaStencils: Advanced Multigrid Solver Generation. Software for Exascale Computing 2020: 405-452 - [i12]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig:
AnyHLS: High-Level Synthesis with Partial Evaluation. CoRR abs/2002.05796 (2020) - [i11]Muhammad Sabih, Frank Hannig, Jürgen Teich:
Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks. CoRR abs/2008.09072 (2020) - [i10]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: Wedding of OpenVX and DSL-based Code Generation. CoRR abs/2008.11476 (2020)
2010 – 2019
- 2019
- [b3]Sascha Roloff, Frank Hannig, Jürgen Teich:
Modeling and Simulation of Invasive Applications and Architectures. Computer Architecture and Design Methodologies, Springer 2019, ISBN 978-981-13-8386-1, pp. i-xv, 1-168 - [j29]Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich:
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. J. Comput. 14(8): 541-556 (2019) - [j28]Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich:
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. 5: 1-20 (2019) - [c118]Jörg Fickenscher, Frank Hannig, Jürgen Teich:
DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs. ARCS 2019: 71-86 - [c117]Marcel Brand, Michael Witterauf, Frank Hannig, Jürgen Teich:
Anytime instructions for programmable accuracy floating-point arithmetic. CF 2019: 215-219 - [c116]Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich:
From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. CGO 2019: 242-253 - [c115]Michael Witterauf, Frank Hannig, Jürgen Teich:
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. MEMOCODE 2019: 8:1-8:10 - [c114]Stefan Groth, Christian Schmitt, Jürgen Teich, Frank Hannig:
SYCL Code Generation for Multigrid Methods. SCOPES 2019: 41-44 - 2018
- [b2]Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich:
Symbolic Parallelization of Nested Loop Programs. Springer 2018, ISBN 978-3-319-73908-3, pp. I-XII, 1-176 - [j27]Dietmar Fey, Frank Hannig:
Special issue on heterogeneous real-time image processing. J. Real Time Image Process. 14(3): 513-515 (2018) - [j26]Christian Schmitt, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Christian Lengauer:
Automating the Development of High-Performance Multigrid Solvers. Proc. IEEE 106(11): 1969-1984 (2018) - [j25]Christian Schmitt, Moritz Schmid, Sebastian Kuckuk, Harald Köstler, Jürgen Teich, Frank Hannig:
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Parallel Process. Lett. 28(4): 1850016:1-1850016:21 (2018) - [j24]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. 17(2): 31:1-31:27 (2018) - [j23]Oliver Reiche, M. Akif Ozkan, Frank Hannig, Jürgen Teich, Moritz Schmid:
Loop Parallelization Techniques for FPGA Accelerator Synthesis. J. Signal Process. Syst. 90(1): 3-27 (2018) - [c113]Ayesha Afzal, Christian Schmitt, Samer Alhaddad, Yevgen Grynko, Jürgen Teich, Jens Förstner, Frank Hannig:
Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study. ASAP 2018: 1-8 - [c112]Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP 2018: 1-9 - [c111]Jörg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa:
Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. DATE 2018: 443-448 - [c110]Tobias Kenter, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, Christian Plessl:
OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. FCCM 2018: 189-196 - [c109]Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich:
Automatic Kernel Fusion for Image Processing DSLs. SCOPES 2018: 76-85 - [c108]Jörg Fickenscher, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa:
Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. VEHITS 2018: 298-306 - 2017
- [j22]Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Ulrich Rüde, Christian Lengauer:
A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms. Int. J. Comput. Sci. Eng. 14(2): 150-163 (2017) - [j21]Frank Hannig, João M. P. Cardoso, Dietmar Fey:
Introduction to the special issue on architecture of computing systems. J. Syst. Archit. 77: 1-2 (2017) - [j20]Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel:
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Trans. Computers 66(3): 488-501 (2017) - [j19]Didem Unat, Anshu Dubey, Torsten Hoefler, John Shalf, Mark James Abraham, Mauro Bianco, Bradford L. Chamberlain, Romain Cledat, H. Carter Edwards, Hal Finkel, Karl Fuerlinger, Frank Hannig, Emmanuel Jeannot, Amir Kamil, Jeff Keasler, Paul H. J. Kelly, Vitus J. Leung, Hatem Ltaief, Naoya Maruyama, Chris J. Newburn, Miquel Pericàs:
Trends in Data Locality Abstractions for HPC Systems. IEEE Trans. Parallel Distributed Syst. 28(10): 3007-3020 (2017) - [j18]Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, Dibyendu Ghoshal:
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. 89(2): 225-242 (2017) - [c107]M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich:
Hardware design and analysis of efficient loop coarsening and border handling for image processing. ASAP 2017: 155-163 - [c106]Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich:
Efficiency in ILP processing by using orthogonality. ASAP 2017: 207 - [c105]Sascha Roloff, Frank Hannig, Jürgen Teich:
High performance network-on-chip simulation by interval-based timing predictions. ESTIMedia 2017: 2-11 - [c104]Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig:
Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). ICCAD 2017: 1026-1033 - [c103]Jörg Fickenscher, Sebastian Reinhart, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa:
Convoy tracking for ADAS on embedded GPUs. Intelligent Vehicles Symposium 2017: 959-965 - [c102]Oliver Reiche, Christof Kobylko, Frank Hannig, Jürgen Teich:
Auto-vectorization for image processing DSLs. LCTES 2017: 21-30 - [c101]Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich:
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC 2017: 5-12 - [c100]Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich:
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig 2017: 1-3 - [c99]Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig 2017: 1-8 - [c98]Michael Witterauf, Frank Hannig, Jürgen Teich:
Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. RSP 2017: 9-15 - 2016
- [j17]Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel:
Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. 58(6): 297-307 (2016) - [j16]Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
HIPAcc: A Domain-Specific Language and Compiler for Image Processing. IEEE Trans. Parallel Distributed Syst. 27(1): 210-224 (2016) - [c97]Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP 2016: 58-66 - [c96]M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich:
FPGA-based accelerator design from a domain-specific language. FPL 2016: 1-9 - [c95]Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, Jürgen Teich:
Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs. HLDVT 2016: 70-77 - [c94]Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, Jürgen Teich:
ActorX10: an actor library for X10. X10@PLDI 2016: 24-29 - [c93]Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich:
Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS 2016: 211-218 - [p5]Dirk Koch, Daniel Ziener, Frank Hannig:
FPGA Versus Software Programming: Why, When, and How? FPGAs for Software Programmers 2016: 1-21 - [p4]Frank Hannig:
A Quick Tour of High-Level Synthesis Solutions for FPGAs. FPGAs for Software Programmers 2016: 49-59 - [p3]Moritz Schmid, Christian Schmitt, Frank Hannig, Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Adrián Cristal:
Big Data and HPC Acceleration with Vivado HLS. FPGAs for Software Programmers 2016: 115-136 - [p2]Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich:
HIPAcc. FPGAs for Software Programmers 2016: 205-223 - [p1]Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Harald Köstler, Ulrich Rüde, Christian Lengauer:
Systems of Partial Differential Equations in ExaSlang. Software for Exascale Computing 2016: 47-67 - [e4]Dirk Koch, Frank Hannig, Daniel Ziener:
FPGAs for Software Programmers. Springer 2016, ISBN 978-3-319-26406-6 [contents] - [e3]Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich:
Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings. Lecture Notes in Computer Science 9637, Springer 2016, ISBN 978-3-319-30694-0 [contents] - 2015
- [j15]Frank Hannig, Andreas Herkersdorf:
Introduction to the Special Issue on Testing, prototyping, and debugging of multi-core architectures. J. Syst. Archit. 61(10): 600 (2015) - [j14]Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich, Dietmar Fey:
Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. 61(10): 646-658 (2015) - [j13]Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. 61(10): 668-680 (2015) - [c92]Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer:
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS 2015: 1-8 - [c91]Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich:
Loop coarsening in C-based High-Level Synthesis. ASAP 2015: 166-173 - [c90]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari:
On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP 2015: 194-201 - [c89]Sascha Roloff, David Schafhauser, Frank Hannig, Jürgen Teich:
Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. DAC 2015: 44:1-44:6 - [c88]Sascha Roloff, Stefan Wildermann, Frank Hannig, Jürgen Teich:
Invasive computing for predictable stream processing: a simulation-based case study. ESTIMedia 2015: 1-2 - [c87]Éricles Sousa, Frank Hannig, Jürgen Teich:
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. IESS 2015: 218-229 - [c86]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE 2015: 188-197 - [c85]Éricles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann:
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. SCOPES 2015: 121-124 - [i9]Frank Hannig, Dietmar Fey, Anton Lokhmotov:
Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015). CoRR abs/1502.07241 (2015) - [i8]Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig, Jürgen Teich, Dietmar Fey:
Automatic Optimization of Hardware Accelerators for Image Processing. CoRR abs/1502.07448 (2015) - [i7]Frank Hannig, Dirk Koch, Daniel Ziener:
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). CoRR abs/1508.06320 (2015) - 2014
- [j12]Richard Membarth, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich, Markus Stürmer, Harald Köstler:
Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language. J. Parallel Distributed Comput. 74(12): 3191-3201 (2014) - [j11]Alexander Grebhahn, Sebastian Kuckuk, Christian Schmitt, Harald Köstler, Norbert Siegmund, Sven Apel, Frank Hannig, Jürgen Teich:
Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror. Parallel Process. Lett. 24(3) (2014) - [j10]Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche:
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. 13(4s): 133:1-133:29 (2014) - [j9]Srinivas Boppu, Frank Hannig, Jürgen Teich:
Compact Code Generation for Tightly-Coupled Processor Arrays. J. Signal Process. Syst. 77(1-2): 5-29 (2014) - [j8]Jürgen Teich, Alexandru Tanase, Frank Hannig:
Symbolic Mapping of Loop Programs onto Processor Arrays. J. Signal Process. Syst. 77(1-2): 31-59 (2014) - [c84]Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich:
Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. ACSSC 2014: 398-403 - [c83]Sascha Roloff, Frank Hannig, Jürgen Teich:
Towards Actor-oriented Programming on PGAS-based Multicore Architectures. ARCS Workshops 2014: 1-2 - [c82]Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal:
Domain-specific augmentations for High-Level Synthesis. ASAP 2014: 173-177 - [c81]Oliver Reiche, Moritz Schmid, Frank Hannig, Richard Membarth, Jürgen Teich:
Code generation from a domain-specific language for C-based HLS of hardware accelerators. CODES+ISSS 2014: 17:1-17:10 - [c80]Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour:
Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP 2014: 1-8