default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDavid Bol
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
Journal Articles
- 2024
[j45]Rémi Dekimpe
, David Bol:
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2507-2517 (2024)- 2023
- [j44]Louis Golard, Jérôme Louveaux, David Bol:
Evaluation and projection of 4G and 5G RAN energy footprints: the case of Belgium for 2020-2025. Ann. des Télécommunications 78(5-6): 313-327 (2023) - [j43]Marco Gonzalez, Pengcheng Xu, Rémi Dekimpe, Maxime Schramme, Ivan Stupia, Thibault Pirson, David Bol:
Technical and Ecological Limits of 2.45-GHz Wireless Power Transfer for Battery-Less Sensors. IEEE Internet Things J. 10(17): 15431-15442 (2023) - [j42]Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol:
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization. IEEE J. Solid State Circuits 58(7): 1871-1884 (2023) - [j41]Martin Lefebvre, Denis Flandre, David Bol:
A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI. IEEE J. Solid State Circuits 58(8): 2239-2251 (2023) - [j40]Mathieu Xhonneux, Jérôme Louveaux, David Bol:
A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios. IEEE Open J. Circuits Syst. 4: 165-175 (2023) - [j39]Charlotte Frenkel, David Bol, Giacomo Indiveri:
Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial Intelligence. Proc. IEEE 111(6): 623-652 (2023) - [j38]Adrian Kneip, David Bol:
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1311-1323 (2023) - [j37]Maxime Schramme, David Bol:
UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2464-2477 (2023) - [j36]Pengcheng Xu, Denis Flandre, David Bol:
Analysis and Design of RF Energy-Harvesting Systems With Impedance-Aware Rectifier Sizing. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 361-365 (2023) - 2022
- [j35]Mathieu Xhonneux, Orion Afisiadis, David Bol, Jérôme Louveaux:
A Low-Complexity LoRa Synchronization Algorithm Robust to Sampling Time Offsets. IEEE Internet Things J. 9(5): 3756-3769 (2022) - [j34]Rémi Dekimpe, David Bol:
ECG Arrhythmia Classification on an Ultra-Low-Power Microcontroller. IEEE Trans. Biomed. Circuits Syst. 16(3): 456-466 (2022) - [j33]Maxime Schramme, Léopold Van Brandt, Denis Flandre, David Bol:
Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 1883-1895 (2022) - [j32]Léopold Van Brandt, Roghayeh Saeidi, David Bol, Denis Flandre:
Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2767-2780 (2022) - [j31]Martin Lefebvre, David Bol:
A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm With 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3237-3250 (2022) - 2021
- [j30]Pengcheng Xu, Denis Flandre, David Bol:
A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform. IEEE J. Solid State Circuits 56(6): 1816-1826 (2021) - [j29]David Bol, Maxime Schramme, Ludovic Moreau, Pengcheng Xu, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre:
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. IEEE J. Solid State Circuits 56(7): 2256-2269 (2021) - [j28]Joachim Tapparel, Mathieu Xhonneux, David Bol, Jérôme Louveaux, Andreas Burg:
Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers. IEEE Open J. Commun. Soc. 2: 2725-2738 (2021) - [j27]Adrian Kneip, David Bol:
Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 1931-1944 (2021) - [j26]Rémi Dekimpe, David Bol:
A Configurable ULP Instrumentation Amplifier With Pareto-Optimal Power-Noise Trade-Off Achieving 1.93 NEF in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2272-2276 (2021) - 2020
- [j25]Itamar Levi, Davide Bellizia, David Bol, François-Xavier Standaert:
Ask Less, Get More: Side-Channel Signal Hiding, Revisited. IEEE Trans. Circuits Syst. 67-I(12): 4904-4917 (2020) - 2019
- [j24]Remi Dekimpe, Pengcheng Xu, Maxime Schramme, Pierre Gérard, Denis Flandre, David Bol:
A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer. Integr. 67: 8-18 (2019) - [j23]Pengcheng Xu, Denis Flandre, David Bol:
Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors. IEEE J. Solid State Circuits 54(10): 2717-2729 (2019) - [j22]Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat, David Bol:
A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS. IEEE Trans. Biomed. Circuits Syst. 13(1): 145-158 (2019) - [j21]Charlotte Frenkel, Jean-Didier Legat, David Bol:
MorphIC: A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning. IEEE Trans. Biomed. Circuits Syst. 13(5): 999-1010 (2019) - 2018
- [j20]François Stas, David Bol:
A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 935-945 (2018) - [j19]Cecilia Gimeno, Denis Flandre, David Bol:
Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 2015-2023 (2018) - [j18]Javier Aguirre, David Bol, Denis Flandre, Carlos Sánchez-Azqueta, Santiago Celma:
A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks. IEEE Trans. Ind. Electron. 65(2): 1518-1525 (2018) - [j17]Cecilia Gimeno, David Bol, Denis Flandre:
Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1807-1811 (2018) - 2017
- [j16]Guerric de Streel, François Stas, Thibaut Gurne, François Durant, Charlotte Frenkel, Andreia Cathelin, David Bol:
SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping. IEEE J. Solid State Circuits 52(4): 1163-1177 (2017) - 2016
- [j15]Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol:
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. Microelectron. J. 57: 76-86 (2016) - 2015
- [j14]Numa Couniot, Guerric de Streel, François Botman, Angelo Kuti Lusala, Denis Flandre, David Bol:
A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs. IEEE J. Solid State Circuits 50(10): 2419-2430 (2015) - [j13]Numa Couniot, David Bol, Olivier Poncelet, Laurent A. Francis, Denis Flandre:
A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz. IEEE Trans. Circuits Syst. II Express Briefs 62-II(2): 159-163 (2015) - 2014
- [j12]Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville:
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. J. Low Power Electron. 10(1): 118-126 (2014) - [j11]Julien De Vos, Denis Flandre, David Bol:
A Sizing Methodology for On-Chip Switched-Capacitor DC/DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1597-1606 (2014) - [j10]Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, Israel Koren:
A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks. IEEE Trans. Emerg. Top. Comput. 2(2): 107-118 (2014) - [j9]François Botman, David Bol, Jean-Didier Legat, Kaushik Roy:
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2561-2570 (2014) - 2013
- [j8]David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat:
SleepWalker: A 25-MHz 0.4-V Sub-mm2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes. IEEE J. Solid State Circuits 48(1): 20-32 (2013) - 2012
- [j7]Julien De Vos, Denis Flandre, David Bol:
Pushing Adaptive Voltage Scaling Fully on Chip. J. Low Power Electron. 8(1): 95-112 (2012) - [j6]David Bol, Cédric Hocquet, Francesco Regazzoni:
A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 947-951 (2012) - 2011
- [j5]Cédric Hocquet, Dina Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, François-Xavier Standaert:
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. J. Cryptogr. Eng. 1(1): 79-86 (2011) - 2010
- [j4]David Bol, Denis Flandre, Jean-Didier Legat:
Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels. ACM Trans. Design Autom. Electr. Syst. 16(1): 2:1-2:26 (2010) - 2009
- [j3]David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
Interests and Limitations of Technology Scaling for Subthreshold Logic. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1508-1519 (2009) - 2007
- [j2]David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat:
Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. J. Multiple Valued Log. Soft Comput. 13(1-2): 61-78 (2007) - 2006
- [j1]Philippe Manet, Renaud Ambroise, David Bol, Marc Baltus, Jean-Didier Legat:
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. J. Low Power Electron. 2(1): 95-104 (2006)
Conference and Workshop Papers
- 2024
- [c58]Martin Lefebvre, David Bol:
A Mixed-Signal Near-Sensor Convolutional Imager SoC with Charge-Based 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection. CICC 2024: 1-2 - [c57]Pol Maistriaux, Marco Gonzalez, Jérôme Louveaux, David Bol:
Leveraging a Digital Chirp Spread Spectrum Detector for LPWAN Wake-Up Receivers. CSNDSP 2024: 638-643 - [c56]Marco Gonzalez, Pol Maistriaux, David Bol:
A Narrowband RF Front End in 22-nm FD-SOI Featuring a Programmable Low-Noise Amplifier with a Configurable Noise-Power Trade-Off. ISCAS 2024: 1-5 - 2023
- [c55]Marco Gonzalez, David Bol:
Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW. DATE 2023: 1-6 - 2022
- [c54]Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol:
A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization. ESSCIRC 2022: 157-160 - [c53]Rémi Dekimpe, David Bol:
Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-End. ESSCIRC 2022: 445-448 - [c52]Martin Lefebvre, Denis Flandre, David Bol:
A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOI. ESSCIRC 2022: 469-472 - [c51]Thibault Pirson, Thibault P. Delhaye, Alex Pip, Grégoire Le Brun, Jean-Pierre Raskin, David Bol:
The Environmental Footprint of IC Production: Meta-Analysis and Historical Trends. ESSDERC 2022: 352-355 - [c50]Pol Maistriaux, Thibault Pirson, Maxime Schramme, Jérôme Louveaux, David Bol:
Modeling the Carbon Footprint of Battery-Powered IoT Sensor Nodes for Environmental-Monitoring Applications. IOT 2022: 9-16 - 2021
- [c49]Mathieu Xhonneux, Joachim Tapparel, Péter Scheepers, Orion Afisiadis, Alexios Balatsoukas-Stimming, David Bol, Jérôme Louveaux, Andreas Burg:
A Two-User Successive Interference Cancellation LoRa Receiver with Soft-Decoding. ACSCC 2021: 948-953 - [c48]David Bol, Thibault Pirson, Rémi Dekimpe:
Moore's Law and ICT Innovation in the Anthropocene. DATE 2021: 19-24 - [c47]Martin Lefebvre, Ludovic Moreau, Rémi Dekimpe, David Bol:
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection. ISSCC 2021: 118-120 - [c46]Alicia Klinefelter, Huichu Liu, Luca Benini, Yvain Thonnart, Keith A. Bowman, Kathy Wilcox, David Bol, Alvin Loke, Ofer Shacham:
SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. ISSCC 2021: 539-540 - [c45]Mathieu Xhonneux, Jérôme Louveaux, David Bol:
Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller. SiPS 2021: 105-110 - [c44]Rémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol:
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. VLSI Circuits 2021: 1-2 - 2020
- [c43]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. ISCAS 2020: 1-5 - 2019
- [c42]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning. ISCAS 2019: 1-5 - [c41]Ludovic Moreau, Rémi Dekimpe, David Bol:
A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. ISCAS 2019: 1-4 - [c40]David Bol, Maxime Schramme, Ludovic Moreau, Thomas Haine, Pengcheng Xu, Charlotte Frenkel, Remi Dekimpe, François Stas, Denis Flandre:
A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. ISSCC 2019: 322-324 - 2018
- [c39]Pengcheng Xu, Denis Flandre, David Bol:
Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors. A-SSCC 2018: 107-110 - [c38]Dina Kamel, Davide Bellizia, François-Xavier Standaert, Denis Flandre, David Bol:
Demonstrating an LPPN Processor. ASHES@CCS 2018: 18-23 - [c37]Thomas Haine, Johan Segers, Denis Flandre, David Bol:
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics. DATE 2018: 195-200 - [c36]Cecilia Gimeno, Denis Flandre, David Bol:
Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI. LASCAS 2018: 1-4 - [c35]Remi Dekimpe, Pengcheng Xu, Maxime Schramme, Denis Flandre, David Bol:
A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer. PATMOS 2018: 68-75 - 2017
- [c34]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors. BioCAS 2017: 1-4 - [c33]Thomas Haine, Quoc-Khoi Nguyen, François Stas, Ludovic Moreau, Denis Flandre, David Bol:
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. ESSCIRC 2017: 312-315 - [c32]Charlotte Frenkel, Giacomo Indiveri, Jean-Didier Legat, David Bol:
A fully-synthesized 20-gate digital spike-based synapse with embedded online learning. ISCAS 2017: 1-4 - [c31]François Stas, David Bol:
Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits. ISCAS 2017: 1-4 - [c30]François Stas, David Bol:
A 0.4V 0.08fJ/cycle retentive True-Single-Phase-Clock 18T Flip-Flop in 28nm FDSOI CMOS. ISCAS 2017: 1-4 - [c29]Thomas Mesquida, Alexandre Valentian, David Bol, Edith Beigné:
Architecture exploration of a fixed point computation unit using precise timing spiking neurons. PATMOS 2017: 1-8 - 2016
- [c28]Thomas Haine, François Stas, Guerric de Streel, Cecilia Gimeno, Denis Flandre, David Bol:
CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array. ICDSC 2016: 155-159 - [c27]François Stas, Guerric de Streel, David Bol:
Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools. NEWCAS 2016: 1-4 - [c26]Dina Kamel, Guerric de Streel, Santos Merino Del Pozo, Kashif Nawaz, François-Xavier Standaert, Denis Flandre, David Bol:
Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers. SPACE 2016: 233-248 - [c25]Charlotte Frenkel, Jean-Didier Legat, David Bol:
Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications. VLSI-SoC 2016: 1-6 - [c24]Guerric de Streel, François Stas, Thibaut Gurne, François Durant, Charlotte Frenkel, David Bol:
SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape. VLSI Circuits 2016: 1-2 - 2015
- [c23]David Bol, El Hafed Boufouss, Denis Flandre, Julien De Vos:
A 0.48mm2 5μW-10mW indoor/outdoor PV energy-harvesting management unit in a 65nm SoC based on a single bidirectional multi-gain/multi-mode switched-cap converter with supercap storage. ESSCIRC 2015: 241-244 - [c22]Ahmed T. Elthakeb, Thomas Haine, Denis Flandre, Yehea Ismail, Hamdy Abd Elhamid, David Bol:
Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. ISCAS 2015: 1414-1417 - [c21]Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester:
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC 2015: 1-3 - [c20]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications. ReCoSoC 2015: 1-7 - 2014
- [c19]François Botman, Julien De Vos, Sebastien Bernard, François Stas, Jean-Didier Legat, David Bol:
Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes. ISCAS 2014: 1207-1210 - [c18]Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol:
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. PATMOS 2014: 1-7 - [c17]David Bol, Guerric de Streel, François Botman, Angelo Kuti Lusala, Numa Couniot:
A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range. VLSIC 2014: 1-2 - 2013
- [c16]Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat:
An efficient metric of setup time for pulsed flip-flops based on output transition time. ICICDT 2013: 9-12 - [c15]Guerric de Streel, David Bol:
Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology. ISLPED 2013: 255-260 - 2012
- [c14]Stéphanie Kerckhof, François Durvaux, Cédric Hocquet, David Bol, François-Xavier Standaert:
Towards Green Cryptography: A Comparison of Lightweight Ciphers from the Energy Viewpoint. CHES 2012: 390-407 - [c13]David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat:
A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes. ISSCC 2012: 490-492 - 2011
- [c12]Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, Israel Koren:
Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation. RFIDSec 2011: 48-60 - 2010
- [c11]Dina Kamel, Cédric Hocquet, François-Xavier Standaert, Denis Flandre, David Bol:
Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits. ESSCIRC 2010: 518-521 - [c10]David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat:
The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic. ESSCIRC 2010: 522-525 - [c9]David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat:
Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. ISCAS 2010: 1484-1487 - 2009
- [c8]David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat:
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. ISLPED 2009: 3-8 - [c7]David Bol, Denis Flandre, Jean-Didier Legat:
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. ISLPED 2009: 21-26 - 2008
- [c6]David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
Analysis and minimization of practical energy in 45nm subthreshold logic circuits. ICCD 2008: 294-300 - [c5]David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
Impact of Technology Scaling on Digital Subthreshold Circuits. ISVLSI 2008: 179-184 - 2007
- [c4]David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices. ICECS 2007: 1404-1407 - 2006
- [c3]Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat:
Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards. ASAP 2006: 347-353 - [c2]David Bol, Jean-Didier Legat, José M. Quintana, Maria José Avedillo:
Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. ICECS 2006: 1049-1052 - 2005
- [c1]Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat:
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. PATMOS 2005: 19-29
Informal and Other Publications
- 2024
- [i12]Ludmila Courtillat-Piazza, Thibault Pirson, Louis Golard, David Bol:
A Cradle-to-Gate Life Cycle Analysis of Bitcoin Mining Equipment Using Sphera LCA and ecoinvent Databases. CoRR abs/2401.17512 (2024) - [i11]Martin Lefebvre, David Bol:
A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-μm Bulk and 22-nm FD-SOI. CoRR abs/2406.04741 (2024) - [i10]Martin Lefebvre, David Bol:
A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11-μm Bulk and 22-nm FD-SOI. CoRR abs/2406.09104 (2024) - 2023
- [i9]Martin Lefebvre, Denis Flandre, David Bol:
A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI. CoRR abs/2302.04504 (2023) - 2022
- [i8]Martin Lefebvre, David Bol:
A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm with 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs. CoRR abs/2202.01751 (2022) - [i7]Gauthier Roussilhe, Thibault Pirson, Mathieu Xhonneux, David Bol:
From Silicon Shield to Carbon Lock-in ? The Environmental Footprint of Electronic Components Manufacturing in Taiwan (2015-2020). CoRR abs/2209.12523 (2022) - 2021
- [i6]Thibault Pirson, David Bol:
Assessing the embodied carbon footprint of IoT edge devices with a bottom-up life-cycle approach. CoRR abs/2105.02082 (2021) - [i5]Charlotte Frenkel, David Bol, Giacomo Indiveri:
Bottom-Up and Top-Down Neural Processing Systems Design: Neuromorphic Intelligence as the Convergence of Natural and Artificial Intelligence. CoRR abs/2106.01288 (2021) - 2020
- [i4]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. CoRR abs/2005.06318 (2020) - 2019
- [i3]Charlotte Frenkel, Jean-Didier Legat, David Bol:
MorphIC: A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning. CoRR abs/1904.08513 (2019) - [i2]Charlotte Frenkel, Martin Lefebvre, David Bol:
Learning without feedback: Direct random target projection as a feedback-alignment algorithm with layerwise feedforward training. CoRR abs/1909.01311 (2019) - 2018
- [i1]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A 0.086-mm2 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS. CoRR abs/1804.07858 (2018)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-11 18:22 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
