"A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode ..."

Ludovic Moreau, Rémi Dekimpe, David Bol (2019)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2019.8702680

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/MoreauDB19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/MoreauDB19
Ludovic Moreau, Rémi Dekimpe, David Bol:
A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. ISCAS 2019: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.