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ORCIDJournal of Low Power Electronics, Volume 8
Volume 8, Number 1, February 2012
- Jean-Michel Portal, Marc Bocquet, Damien Deleruyelle
, Christophe Muller:
Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications. 1-10 - Masoud Daneshtalab, Masoumeh Kamali, Masoumeh Ebrahimi, Siamak Mohammadi, Ali Afzali-Kusha, Juha Plosila:
Adaptive Input-Output Selection Based On-Chip Router Architecture. 11-29 - Ge Chen, Saeid Nooshabadi:
Optimization of On-Chip Interconnect Signaling for Low Energy and High Performance. 30-38 - Rohit Dhiman, Rajeevan Chandel:
Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications. 39-46 - Gabriel A. Rincón-Mora, Andres A. Blanco, Justin P. Vogt:
A 1.3-μW, 0.6-μm CMOS Current-Frequency Analog-Digital Converter for Implantable Blood-Glucose Monitors. 47-57 - Vyasa Sai, Ajay Ogirala, Marlin H. Mickle:
Low-Power Data Driven Symbol Decoder for a UHF Passive RFID Tag. 58-62 - Ming-Hung Chang, Shang-Yuan Lin, Wei Hwang:
A 0.4 V 520 nW 990 μm2 Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS. 63-72 - Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu, Bei Cao:
Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost. 73-81 - Nadine Azémard, Marc Belleville:
Selected Articles from the VARI 2011 Workshop. 82 - Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc:
Impact of Power Consumption and Temperature on Processor Lifetime Reliability. 83-94 - Julien De Vos, Denis Flandre, David Bol:
Pushing Adaptive Voltage Scaling Fully on Chip. 95-112 - Smriti Joshi, Anne Lombardot, Philippe Flatresse, Carmelo D'Agostino, Andre Juge, Edith Beigné, Stéphane Girard:
Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations. 113-124 - J. Mazurier, Olivier Weber, François Andrieu, Alain Toffoli, Olivier Thomas, Fabienne Allain, Jean-Philippe Noel, Marc Belleville, Olivier Faynot, T. Poiroux:
Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below. 125-132
Volume 8, Number 2, April 2012
- Muhammad Tariqus Salam, Fayçal Mounaïm, Dang Khoa Nguyen, Mohamad Sawan:
Low-Power Circuit Techniques for Epileptic Seizures Detection and Subsequent Neurostimulation. 133-145 - Yang Xu, Hu He, Zhizhong Tang:
Energy Consumption Optimized Scheduling Algorithm for Clustered VLIW Architectures. 146-157 - Subhash Chander, Pramod Agarwal, Indra Gupta:
Design and Implementation of Field Programmable Gate Array based Digital Pulse Width Modulator for Synchronous Buck Converter. 158-169 - Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli:
Inter-Plane Communication Methods for 3-D ICs. 170-181 - Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez:
Digital Adaptive Calibration of Multi-Step Analog to Digital Converters. 182-196 - Pierre-Antoine Haddad, Geoffroy Gosset, Denis Flandre:
Design of an Ultra-Low-Power Multi-Stage AC/DC Voltage Rectifier and Multiplier Using a Fully-Automated and Portable Design Methodology. 197-206 - Biswajit Maity, Soumya Gangula, Pradip Mandal:
Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC-DC Converter. 207-222 - Kaushik Bhattacharyya, Pradip Mandal:
Improvement of Performance of Dynamically Reconfigurable Switched Capacitor Based Non-Overlap Rotational Time Interleaved Embedded DC-DC Converter. 223-234 - Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty:
Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits. 235-247 - Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen:
Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns. 248-258
Volume 8, Number 3, June 2012
- Saraju P. Mohanty:
A Special Issue on Power, Parasitics, and Process-Variation (P3) Awareness in Mixed-Signal Design. 259-260 - Narayanan M. Komerath, Rajkumar Pant, Aravinda Kar:
An Architecture Using Lighter-Than-Air Platforms for Retail Power Beaming and Communications. 261-269 - Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. 270-282 - B. Chitti Babu, S. R. Samantaray, M. V. Ashwin Kumar:
Implementation of Smart Battery Charger with Low Power Photo-Voltaic Energy System Using Synchronous Buck Converter. 283-292 - Priyankar Ghosh, Aritra Hazra, Rahul Gonnabhaktula, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul:
POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads. 293-303 - Yang Liu, Ashok Srivastava:
CMOS Phase-Locked Loop Circuits and Hot Carrier Effects. 304-316 - Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos:
Accurate Polynomial Metamodeling-Based Ultra-Fast Bee Colony Optimization of a Nano-CMOS Phase-Locked Loop. 317-328 - Vivek Sharma, Zubair Akhter, Nagendra Prasad Pathak:
2.4-/5.2-GHz Concurrent Dual-Band Wireless Local Area Network Transmitter. 329-335 - Rajiv Soundararajan, Ashok Srivastava:
A Programmable Oversampling CMOS Delta-Sigma Analog-to-Digital Converter for Low-Power Interface Electronics. 336-346 - Sandeep Goud Surya, Sudip Nag, Nikhil M. Duragkar, Dilip Agarwal, Gaurav Chatterjee, Sahir Gandhi, Sheetal Patil, Dinesh Kumar Sharma, V. Ramgopal Rao:
A Low-Power Instrumentation System for Nano-Electro-Mechanical-Sensors for Environmental and Healthcare Applications. 346-352
Volume 8, Number 4, August 2012
- Vinod Viswanath, Rajeev Muralidhar, Harinarayanan Seshadri, Ananth S. Narayan:
Power Management Methods: From Specification and Modeling, to Techniques and Verification. 353-377 - Huang Huang, Vivek Chaturvedi, Guanglei Liu, Gang Quan:
Leakage Aware Scheduling on Maximum Temperature Minimization for Periodic Hard Real-Time Systems. 378-393 - Johann Laurent, André Rossi, Marc Sevaux:
MemExplorer: From C Code to Memory Allocation. 394-402 - Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms. 403-414 - Giuseppe Visalli:
A Bus Switch Coding System with Minimal Hardware Demand. 415-423 - Vinod Viswanath, Jacob A. Abraham:
Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design. 424-439 - Esmaeil Amini, Zahra Jeddi, Ahmed K. F. Khattab, Magdy A. Bayoumi:
A Low-Power Parallel Architecture for Finite Galois Field GF(2m) Arithmetic Operations for Elliptic Curve Cryptography. 440-451 - Priyanka Choudhury, Sambhu Nath Pradhan:
An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding Together. 452-463 - Pradeep S. Nair, Savithra Eratne, Eugene B. John:
Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance. 464-471 - Dao-Ping Wang, Wei Hwang:
A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation. 472-484 - Nicolas Degrenne, Bruno Allard, François Buret, Salah-Eddine Adami, Denis Labrousse, Christian Vollaire, Florent Morel:
A 140 mV Self-Starting 10 mW DC/DC Converter for Powering Low-Power Electronic Devices from Low-Voltage Microbial Fuel Cells. 485-497 - Gang Yang, Patrick Dubus, Daniel Sadarnac:
Design of a High Efficiency, Wide Input Range 500 kHz 25 W LLC Resonant Converter. 498-508 - Vyasa Sai, Ajay Ogirala, Marlin H. Mickle:
Implementation of an Asynchronous Low-Power Small-Area Passive Radio Frequency Identification Design Using Synchronous Tools for Automation Applications. 509-515 - Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti:
Interconnect Aware Test Power Reduction. 516-525 - Jiaoyan Chen, Dilip P. Vasudevan, Michel P. Schellekens, Emanuel M. Popovici:
Ultra Low Power Asynchronous Charge Sharing Logic. 526-534
Volume 8, Number 5, December 2012
- Yang Ge, Yukan Zhang, Parth Malani, Qing Wu, Qinru Qiu:
Low Power Task Scheduling and Mapping for Applications with Conditional Branches on Heterogeneous Multi-Processor System. 535-551 - Abu Asaduzzaman, Govipalagodage H. Gunasekara:
A Way Cache Locking Scheme Supported by Knowledge Based Smart Preload Effective for Low-Power Multicore Electronics. 552-564 - Guanglei Liu, Ming Fan, Gang Quan, Meikang Qiu:
On-Line Predictive Thermal Management Under Peak Temperature Constraints for Practical Multi-Core Platforms. 565-578 - Abdelkrim Kamel Oudjida, Nicolas Chaillet, Ahmed Liacha, Mohamed Lamine Berrandjia:
A New Recursive Multibit Recoding Algorithm for High-Speed and Low-Power Multiplier. 579-594 - Saman Khoshbakht, Amirali Baniasadi:
Leakage-Aware Speculative Branch Target Buffer. 595-603 - Sumanta Pyne, Ajit Pal:
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques. 604-623 - Narges Shahidi, Ali Shafiee, Amirali Baniasadi:
Heterogeneous Interconnect for Low-Power Snoop-Based Chip Multiprocessors. 624-635 - Vyasa Sai, Ajay Ogirala, Marlin H. Mickle:
Serial Data Driven Cyclic Redundancy Check Generator for Low Power RFID Applications. 636-641 - Benjamin V. P. Chong, Li Zhang:
Ćuk Step-Down Converter Design for Optimum Transient Performance and Minimum Ripple. 642-653 - Bo Li, Xuefang Lin-Shi, Bruno Allard:
Low Power Digital Alternative to Analog Control of Step-Down Converter. 654-666 - Valter Sádio, Fabian Rein, Christian Münker, Marcelino B. Santos:
Modeling of Inherent Losses of Fully Integrated Switched Capacitor DC-DC Converters. 667-673 - Aswin Sreedhar, Sandip Kundu, Israel Koren:
On Reliability Trojan Injection and Detection. 674-683 - Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti:
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. 684-695 - Nadine Azémard, Gilles Jacquemod:
Selected Articles from the VARI 2012 Workshop. 696 - Hao Cai, Hervé Petit, Jean-François Naviner:
A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems. 697-705 - Yannick Vaiarello, William Tatinian, Yves Leduc, Nicolas Veau, Gilles Jacquemod:
Ultra-Low-Power Audio Communication System for Cochlear Implant Application. 706-716 - Guillaume Just, Vincenzo Della Marca, Arnaud Régnier, Jean-Luc Ogier, Jérémy Postel-Pellerin, Jean-Michel Portal, Pascal Masson:
Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability. 717-724 - Luciano Lavagno, Patrick Haspel:
Selected Articles from the CDNLive! EMEA 2012 Conference. 725 - Martin Palkovic, Peter Debacker, Prabhat Avasare, Steven Dupont, Tom Vander Aa:
Power Estimation at Different Abstraction Levels for Wireless Baseband Processors. 726-738 - Shane Stelmach, Kaijian Shi, Anthony Hill:
Automation of Switch Insertion and Power Network Generation in 28 nm Power-Switched Designs. 739-745
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