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"8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC ..."

Sylvain Clerc et al. (2015)

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DOI: 10.1109/ISSCC.2015.7062970

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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  - conf/isscc/ClercSACDBBVZCS15
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  - https://dblp.org/rec/conf/isscc/ClercSACDBBVZCS15
Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester:
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC 2015: 1-3

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