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ORCIDIntegration, Volume 67
Volume 67, July 2019
- Naci Pekcokguler
, Günhan Dündar, Catherine Dehollain:
Analysis, modeling and design of a CMOS Super-Regenerative Receiver for implanted medical devices under square and sinusoidal quench signals. 1-7
- Remi Dekimpe, Pengcheng Xu, Maxime Schramme, Pierre Gérard, Denis Flandre, David Bol:
A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer. 8-18
- Jeremy Scerri, Ivan Grech, Edward Gatt, Owen Casha:
Dimensional optimisation of a MEMS BPSK to ASK converter in SOIMUMPs. 19-32
- P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini:
Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs. 33-43
- Andrea Ragni, Giuseppe Sciortino, Marco Sampietro, Giorgio Ferrari, Dario Polli:
Multi-channel lock-in based differential front-end for broadband Raman spectroscopy. 44-49 - Semih Turk, Alexander Schug, Reinhard Viga, Andreas Jupe, Holger Vogt:
Optimization of the dielectric layer for electrowetting on dielectric. 50-59
- Lennart Bamberg, Jan Moritz Joseph, Thilo Pionteck, Alberto García Ortiz:
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment. 60-72
- Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, Raoul Grimoldi, L. Cattaneo:
A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs. 73-81
- Lihuan Wang, Shuyan Jiang, Shuyu Chen, Junshi Wang, Letian Huang:
Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system. 82-94 - Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar:
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems. 95-107 - Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding. 108-120 - Barend Harris, Inpyo Bae, Bernhard Egger:
Architectures and algorithms for on-device user customization of CNNs. 121-133 - Shuyan Jiang, Qiong Wu, Shuyu Chen, Junkai Zhan, Junshi Wang, Masoumeh Ebrahimi, Letian Huang:
Testing aware dynamic mapping for path-centric network-on-chip test. 134-143
- Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach. 144-154 - Asghar Bahramali, Marisa López-Vallejo:
A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage. 155-161
- Engin Afacan, Günhan Dündar:
A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization. 162-169
- Aaron Stillmaker, Bevan M. Baas:
Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" [Integr. VLSI J. 58. (2017) 74-81]. 170
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