"Integration of level shifting in a TSPC flip-flop for low-power robust ..."

François Stas, David Bol (2017)

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DOI: 10.1109/ISCAS.2017.8050571

access: closed

type: Conference or Workshop Paper

metadata version: 2017-10-07

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François Stas, David Bol:
Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits. ISCAS 2017: 1-4

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