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Journal Articles
- 2023
[j20]Sumeet Singh Nagi
, Uneeb Rathore, Krutikesh Sahoo, Tim Ling, Subramanian S. Iyer, Dejan Markovic:
A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration. IEEE J. Solid State Circuits 58(1): 111-123 (2023)- 2022
- [j19]Zhe Wan, Tianyi Wang, Yiming Zhou, Subramanian S. Iyer, Vwani P. Roychowdhury:
Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines. ACM J. Emerg. Technol. Comput. Syst. 18(2): 33:1-33:23 (2022) - 2020
- [j18]Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subramanian S. Iyer, Maryam Shojaei Baghini:
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(5): 1073-1083 (2020) - 2019
- [j17]Subramanian S. Iyer, SivaChandra Jangam, Boris Vaisband:
Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems. IBM J. Res. Dev. 63(6): 5:1-5:16 (2019) - [j16]Yuan Du, Li Du, Xuefeng Gu, Jieqiong Du, X. Shawn Wang, Boyu Hu, Mingzhe Jiang, Xiaoliang Chen, Subramanian S. Iyer, Mau-Chung Frank Chang:
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1811-1819 (2019) - 2018
- [j15]Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer:
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. IEEE J. Solid State Circuits 53(3): 949-960 (2018) - 2017
- [j14]Arvind Kumar, Zhe Wan, Winfried W. Wilcke, Subramanian S. Iyer:
Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration. ACM J. Emerg. Technol. Comput. Syst. 13(3): 45:1-45:21 (2017) - [j13]Liheng Zhu, Yasmine Badr, Shaodi Wang, Subramanian S. Iyer, Puneet Gupta:
Assessing Benefits of a Buried Interconnect Layer in Digital Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 346-350 (2017) - 2016
- [j12]Toshiaki Kirihata, John Golz, Matthew R. Wordeman, Pooja Batra, Gary W. Maier, Norman Robson, Troy L. Graves-abe, Daniel Berger, Subramanian S. Iyer:
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 373-384 (2016) - [j11]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer:
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. IEEE J. Solid State Circuits 51(1): 230-239 (2016) - 2014
- [j10]Subramanian S. Iyer:
Silicon stress: technical perspective. Commun. ACM 57(1): 106 (2014) - 2013
- [j9]Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM. IEEE J. Solid State Circuits 48(4): 940-947 (2013) - [j8]Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM. IEEE J. Solid State Circuits 48(11): 2934-2943 (2013) - 2011
- [j7]Mukta G. Farooq, Subramanian S. Iyer:
3D integration review. Sci. China Inf. Sci. 54(5): 1012-1025 (2011) - [j6]Subramanian S. Iyer, Greg G. Freeman, Colin Brodsky, Anthony I. Chou, Dan Corliss, Sameer H. Jain, Naftali E. Lustig, Vincent McGahay, Shreesh Narasimha, James P. Norum, Karen A. Nummy, Paul C. Parries, Sujatha Sankaran, Chris D. Sheraw, Pushkara Rao Varanasi, Geng Wang, Mary E. Weybright, Xiaojun Yu, Emmanuel Crabbe, Paul D. Agnello:
45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications. IBM J. Res. Dev. 55(3): 5 (2011) - 2009
- [j5]Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer:
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits 44(4): 1216-1226 (2009) - 2008
- [j4]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43(1): 86-95 (2008) - 2005
- [j3]Subramanian S. Iyer, John E. Barth Jr., Paul C. Parries, James P. Norum, James P. Rice, Lyndon R. Logan, Dennis Hoyniak:
Embedded DRAM: Technology platform for the Blue Gene/L chip. IBM J. Res. Dev. 49(2-3): 333-350 (2005) - [j2]Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer:
An 800-MHz embedded DRAM with a concurrent refresh mode. IEEE J. Solid State Circuits 40(6): 1377-1387 (2005) - 2000
- [j1]Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki:
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. IEEE J. Solid State Circuits 35(11): 1673-1679 (2000)
Conference and Workshop Papers
- 2023
- [c28]Yousef Safari, Pooya Aghanoury, Subramanian S. Iyer, Nader Sehatbakhsh, Boris Vaisband:
Hybrid Obfuscation of Chiplet-Based Systems. DAC 2023: 1-6 - [c27]Sepideh Nouri, Subramanian S. Iyer:
An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices. ISSCC 2023: 434-435 - 2022
- [c26]Uneeb Rathore, Sumeet Singh Nagi, Subramanian S. Iyer, Dejan Markovic:
A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration. ISSCC 2022: 52-54 - 2021
- [c25]Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, Puneet Gupta:
Designing a 2048-Chiplet, 14336-Core Waferscale Processor. DAC 2021: 1183-1188 - [c24]Yu-Tao Yang, Subramanian S. Iyer:
Large-Scale Quantum System Design on Nb-based Superconducting Silicon Interconnect Fabric. ISQED 2021: 315 - 2019
- [c23]Saptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar:
Architecting Waferscale Processors - A GPU Case Study. HPCA 2019: 250-263 - [c22]Niloofar Shakoorzadeh, Amir Hanna, Subramanian S. Iyer:
Bilayer Passivation Film for Cu Interconnects on Si Interconnect Fabric. IRPS 2019: 1-5 - [c21]Kannan K. Thankappan, Adeel Ahmad Bajwa, Boris Vaisband, SivaChandra Jangam, Subramanian S. Iyer:
Reliability Evaluation of Silicon Interconnect Fabric Technology. IRPS 2019: 1-5 - [c20]Boris Vaisband, Subramanian S. Iyer:
Global and semi-global communication on Si-IF. NOCS 2019: 15:1-15:5 - [c19]Boris Vaisband, Subramanian S. Iyer:
Communication Considerations for Silicon Interconnect Fabric. SLIP 2019: 1-6 - 2018
- [c18]Saptadeep Pal, Daniel Petrisko, Adeel Ahmad Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar:
A Case for Packageless Processors. HPCA 2018: 466-479 - [c17]Subramanian S. Iyer, Adeel Ahmad Bajwa:
Reliability challenges in advance packaging. IRPS 2018: 4 - [c16]William Whitehead, Steven Moran, Bilwaj Gaonkar, Luke Macyszyn, Subramanian S. Iyer:
A deep learning approach to spine segmentation using a feed-forward chain of pixel-wise convolutional networks. ISBI 2018: 868-871 - [c15]Boris Vaisband, Adeel Ahmad Bajwa, Subramanian S. Iyer:
Network on interconnect fabric. ISQED 2018: 138-143 - 2017
- [c14]Saptadeep Pal, Subramanian S. Iyer, Puneet Gupta:
Advanced Packaging and Heterogeneous Integration to Reboot Computing. ICRC 2017: 1-6 - [c13]Ross M. Walker, Loren Rieth, Subramanian S. Iyer, Adeel Ahmad Bajwa, Jason Silver, Taufiq Ahmed, Naila Tasneem, Mohit Sharma, A. Tye Gardner:
Integrated neural interfaces. MWSCAS 2017: 1045-1048 - [c12]Subramanian S. Iyer:
Heterogeneous SoCs. VLSI-DAT 2017: 1 - 2016
- [c11]Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer:
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits 2016: 1-2 - 2015
- [c10]Subramanian S. Iyer:
Invited talk: Some challenges in scaling 3D ICs to a broader application set. 3DIC 2015: TS1.1.1 - [c9]Chandrasekharan Kothandaraman, X. Chen, Dan Moy, Dallas Lea, Sami Rosenblatt, Faraz Khan, Derek Leu, Toshiaki Kirihata, D. Ioannou, Giuseppe La Rosa, Jeffrey B. Johnson, Norman Robson, Subramanian S. Iyer:
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications. IRPS 2015: 2 - [c8]Mukta G. Farooq, Giuseppe La Rosa, Fen Chen, Prakash Periasamy, Troy L. Graves-abe, Chandrasekharan Kothandaraman, C. Collins, W. Landers, J. Oakley, J. Liu, John Safran, S. Ghosh, S. Mittl, D. Ioannou, Carole Graas, Daniel Berger, Subramanian S. Iyer:
Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability. IRPS 2015: 4 - 2012
- [c7]Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer:
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. ICICDT 2012: 1-4 - [c6]Daniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM. VLSIC 2012: 146-147 - 2011
- [c5]Subramanian S. Iyer, Toshiaki Kirihata, John E. Barth Jr.:
Three Dimensional integration - Considerations for memory applications. CICC 2011: 1-7 - 2008
- [c4]Gregory Uhlmann, Tony Aipperspach, Toshiaki Kirihata, K. Chandrasekharan, Yan Zun Li, Chris Paone, Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian S. Iyer:
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS. ISSCC 2008: 406-407 - [c3]Wei Kong, Paul C. Parries, G. Wang, Subramanian S. Iyer:
Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation. ITC 2008: 1-7 - 2007
- [c2]Norman Robson, John Safran, Chandrasekharan Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, Alan Leslie, Dan Moy, Toshiaki Kirihata, Subramanian S. Iyer:
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips. CICC 2007: 799-804 - [c1]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC 2007: 486-617
Informal and Other Publications
- 2020
- [i1]Zhe Wan, Tianyi Wang, Yiming Zhou, Subramanian S. Iyer, Vwani P. Roychowdhury:
Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines. CoRR abs/2008.02400 (2020)
Coauthor Index
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