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ORCIDBabar A. Khan
Person information
- affiliation: IBM Systems and Technology Group, Poughkeepsie, NY, USA
- affiliation (PhD 1984): Massachusetts Institute of Technology, Cambridge, MA, USA
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2010 – 2019
- 2016
[j3]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan
, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer:
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. IEEE J. Solid State Circuits 51(1): 230-239 (2016)
2000 – 2009
- 2008
- [j2]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43(1): 86-95 (2008) - 2007
- [c1]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC 2007: 486-617 - 2005
- [j1]Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer:
An 800-MHz embedded DRAM with a concurrent refresh mode. IEEE J. Solid State Circuits 40(6): 1377-1387 (2005)
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