Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"80Kb 10ns read cycle logic Embedded High-K charge trap ..."

Janakiraman Viraraghavan et al. (2016)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2016.7573462

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/ViraraghavanLJC16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/ViraraghavanLJC16
Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer:
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits 2016: 1-2

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.