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Hiroyuki Iwata
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2020 – today
- 2023
- [j4]Senling Wang
, Xihong Zhou
, Yoshinobu Higami
, Hiroshi Takahashi
, Hiroyuki Iwata
, Yoichi Maeda
, Jun Matsushima
:
Test Point Insertion for Multi-Cycle Power-On Self-Test. ACM Trans. Design Autom. Electr. Syst. 28(3): 46:1-46:21 (2023) - [c11]Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee:
A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy. ITC 2023: 1-10 - 2021
- [c10]Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
A Power Reduction Method for Scan Testing in Ultra-Low Power Designs. ATS 2021: 141 - 2020
- [j3]Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. IEICE Trans. Inf. Syst. 103-D(11): 2289-2301 (2020)
2010 – 2019
- 2018
- [j2]Senling Wang
, Yoshinobu Higami
, Hiroshi Takahashi
, Hiroyuki Iwata
, Jun Matsushima:
Automotive Functional Safety Assurance by POST with Sequential Observation. IEEE Des. Test 35(3): 39-45 (2018) - [c9]Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. ATS 2018: 155-160 - [c8]Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. ETS 2018: 1-2 - 2017
- [c7]Jongseung Lee, Nobutaka Mukae, Jumpei Arata, Hiroyuki Iwata, Keiji Iramina, Koji Iihara, Makoto Hashizume:
A multichannel-near-infrared-spectroscopy-triggered robotic hand rehabilitation system for stroke patients. ICORR 2017: 158-163 - 2016
- [c6]Hiroyuki Iwata, Jun Matsushima:
Multi-configuration Scan Structure for Various Purposes. ATS 2016: 131 - [c5]Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima:
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. ATS 2016: 209-214 - 2012
- [c4]Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura:
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms. Asian Test Symposium 2012: 1 - 2011
- [c3]Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer:
Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium 2011: 84-89
2000 – 2009
- 2008
- [j1]Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi:
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1535-1544 (2008) - 2007
- [c2]Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara:
A DFT Method for Time Expansion Model at Register Transfer Level. DAC 2007: 682-687 - 2005
- [c1]Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara:
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium 2005: 306-311
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