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ORCID18th VLSI Design 2005: Kolkata, India
- 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India. IEEE Computer Society 2005, ISBN 0-7695-2264-5
Tutorials
- Pradip Bose:
Power-Aware, Reliable Microprocessor Design. 3-6 - Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani:
High-Speed Interconnect Technology: On-Chip and Off-Chip. 7 - R. D. (Shawn) Blanton, Subhasish Mitra:
Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. 8-9 - Atul Jain, Anindya Saha
, Jagdish Rao:
SoC Design Methodology: A Practical Approach. 10-11 - Abhijit Chatterjee, Ali Keshavarzi, Amit Patra, Siddhartha Mukhopadhyay:
Test Methodologies in the Deep Submicron Era - Analog, Mixed-Signal, and RF. 12-13 - Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea:
Recent Advances in Verification, Equivalence Checking and SAT-Solvers. 14 - A. B. Bhattacharyya:
Compact MOSFET Models for Low Power Analog CMOS Design. 15 - D. Mukhopadhyay, P. K. Basu, V. Ramgopal Rao:
Physics and Technology: Towards Low-Power DSM Design. 16-17 - Luca Benini, Sandeep K. Shukla, Rajesh K. Gupta:
Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems. 18-20
Inaugural Keynote Address
- C. L. Liu:
The High Walls have Crumpled. 21-24
Keynotes
- Ted Vucurevich:
65nm Omnibudsman. 25 - Alan Naumann:
ESL - The Next Leadership Opportunity for India? 26 - Shekhar Borkar:
VLSI Design Challenges for Gigascale Integration. 27
Banquet Speech
- Walden C. Rhines:
Moore's Law is Unconstitutional. 31-32
Plenary Sessions
- Beatrice Fu:
Configurable Processor the Building Block for SOC (System-On-a-Chip). 35- - Janick Bergeron:
Modeling Usable and Reusable Transactors in System Verilog. 36- - Yervant Zorian:
Optimizing SoC Manufacturability. 37-38
Session 1A: Test I
- Irith Pomeranz, Sudhakar M. Reddy:
Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. 41-46 - Haihua Yan, Adit D. Singh:
A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. 47-52 - Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan:
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. 53-58 - Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz:
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. 59-64 - Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. 65-70 - Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das:
Cellular Automata Based Test Structures with Logic Folding. 71-74
Session 1B: Physical Design
- Jens Lienig, Göran Jerke:
Electromigration-Aware Physical Design of Integrated Circuits. 77-82
- Shabbir H. Batterywala, Madhav P. Desai:
Variance Reduction in Monte Carlo Capacitance Extraction. 85-90 - Yibo Wang, Yici Cai, Xianlong Hong:
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. 91-96 - Rajeev Murgai:
Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. 97-102
Session 1C: Embedded Systems
- Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas Navet:
Battery Model for Embedded Systems. 105-110 - Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran:
Rapid Embedded Hardware/Software System Generation. 111-116 - Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar:
A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems. 117-123 - Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim, Thomas Chen:
A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems. 124-129 - Ashok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar:
A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs. 130-133 - Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin:
Implementing LDPC Decoding on Network-on-Chip. 134-137 - Paul Capewell, Ian Watson:
A RISC Hardware Platform for Low Power Java. 138-143
Session 1D: Low Power
- Sabyasachi Mondal, Arijit De, P. K. Biswas:
A Low Power Reprogrammable Parallel Processing VLSI Architecture for Computation of B-Spline Based Medical Image Processing System for Fast Characterization of Tiny Objects Suspended in Cellular Fluid. 147-152 - Saraju P. Mohanty, N. Ranganathan, Karthikeyan Balakrishnan:
Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. 153-158 - Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. 159-164 - Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang:
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. 165-170 - Muhammad Arsalan, Maitham Shams:
Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits. 171-174 - M. S. Bhat, H. S. Jamadagni:
Power Optimization in Current Mode Circuits. 175-180
Session 2A: Formal Verification
- Aarti Gupta, Malay K. Ganai, Pranav Ashar:
Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. 183-188 - Kameshwar Chandrasekar, Michael S. Hsiao:
Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs. 189-194 - Tathagato Rai Dastidar, P. P. Chakrabarti:
A Verification System for Transient Response of Analog Circuits Using Model Checking. 195-200 - Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix:
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. 201-206 - K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti:
A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. 207-212 - Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti:
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules. 213-218
Session 2B: Nanotechnology and Biochips
- Krishnendu Chakrabarty:
Design, Testing, and Applications of Digital Microfluidics-Based Biochips. 221-226
- Rui Zhang, Pallav Gupta, Niraj K. Jha:
Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. 229-234 - Chirasree Pramanik, Tarikul Islam, Hiranmay Saha, Joydeep Bhattacharya, S. Banerjee, Sagnik Dey:
Design, Fabrication, Testing and Simulation of Porous Silicon Based Smart MEMS Pressure Sensor. 235-240 - Kevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin:
A Nanosensor Array-Based VLSI Gas Discriminator. 241-246
Session 2C: Synthesis I
- Avik Chakraborty:
Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays. 249-254 - Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury:
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. 255-260 - Yuanzhong Wan, Maitham Shams:
Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder. 261-266 - Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee:
Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. 267-273 - Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
Integrated On-Chip Storage Evaluation in ASIP Synthesis. 274-279 - Vikram Singh Saun, Preeti Ranjan Panda:
Extracting Exact Finite State Machines from Behavioral SystemC Descriptions. 280-285
Session 2D: RF and Mixed Signal
- Achintya Halder, Soumendu Bhattacharya, Ganesh Srinivasan, Abhijit Chatterjee:
A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode. 289-294 - Tejasvi Das, Clyde Washburn, P. R. Mukund, Steve Howard, Ken Paradis, Jung-Geau Jang, Jan Kolnik, Jeff Burleson:
Effects of Technology and Dimensional Scaling on Input Loss Prediction of RF MOSFETs. 295-300 - Tin Wai Kwan, Maitham Shams:
Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic. 301-306 - Rajarshi Paul, Amit Patra, Shailendra Baranwal, Kaushik Dash:
Design of Second-Order Sub-Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage Applications. 307-312 - Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee:
A 160MSPS 8-Bit Pipeline Based ADC. 313-318 - Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey:
A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC. 319-322
Session 3A: Signal Integrity and Crosstalk
- Atul Katoch, Maurice Meijer, Sanjeev K. Jain:
Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication. 325-329 - Gaurav Kumar Varshney, Sreeram Chandrasekar:
An Efficient Methodology for Noise Characterization. 330-335 - Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney:
Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits. 336-341 - Sachin Shrivastava, Sreeram Chandrasekar:
Crosstalk Noise Analysis at Multiple Frequencies. 342-347 - Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye:
Worst-Case Crosstalk Noise Analysis Based on Dual-Exponential Noise Metrics. 348-353 - Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel:
ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. 354-359
Session 3B: Process Variation
- Vishak Venkatraman, Wayne P. Burleson:
Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects. 362-367 - Charlie Brej, Jim D. Garside:
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. 368-373 - Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. 374-379 - Baohua Wang, Pinaki Mazumder:
Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion. 380-385 - A. Madan, S. C. Bose, P. J. George, Chandra Shekhar:
Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs. 386-391 - R. Srinivasan, Navakanta Bhat:
Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications. 392-396
Session 3C: Design Methodology
- Andreas Hoffmann, Frank Fiedler, Achim Nohl, Surender Parupalli:
A Methodology and Tooling Enabling Application Specific Processor Design. 399-404 - Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury:
An Efficient End to End Design of Rijndael Cryptosystem in 0.18 ? CMOS. 405-410 - Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan:
ADOPT: An Approach to Activity Based Delay Optimization. 411-416 - Srinivasa R. Sridhara, Naresh R. Shanbhag:
Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. 417-422 - Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. 423-426 - R. Gopalakrishnan, Rajat Moona:
Variable Resizing for Area Improvement in Behavioral Synthesis. 427-430
Session 3D: Placement and Routing
- Thomas Eschbach, Wolfgang Günther, Bernd Becker:
Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases. 433-438 - Manish Garg, Laurent Le Cam, Matthieu Gonzalez:
Lithography Driven Layout Design. 439-444 - Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri:
Non-Manhattan Routing Using a Manhattan Router. 445-450 - R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti, Dinesh Bhatia:
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. 451-456 - Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi:
Automatic Device Layout Generation for Analog Layout Retargeting. 457-462 - Suvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran:
Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs. 463-468
Session 4A: Test II
- Wei Li, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy:
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. 471-478 - Aniket, Ravishankar Arunachalam:
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. 479-484 - Anand Gopalan, Tejasvi Das, Clyde Washburn, P. R. Mukund:
An Ultra-Fast, On-Chip BiST for RF Low Noise Amplifiers. 485-490 - Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya:
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design. 491-496 - C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar:
A Framework for Distributed and Hierarchical Design-for-Test. 497-503 - P. Kalpana, K. Gunavathi:
A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets. 504-507
Session 4B: Analog
- Falguni Bala, Tapas Nandy:
Conventional RC oscillators, though offer inexpensiveProgrammable High Frequency RC Oscillator. 511-515 - Jaijeet S. Roychowdhury:
Exact Analytical Equations for Predicting Nonlinear Phase Errors and Jitter in Ring Oscillators. 516-521 - Ashis Maity, R. G. Raghavendra, Pradip Mandal:
On-Chip Voltage Regulator with Improved Transient Response. 522-527 - Mengmeng Ding, Ranga Vemuri:
An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. 528-534 - Abhishek Somani, P. P. Chakrabarti, Amit Patra:
A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits. 535-538 - Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi:
A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch. 539-542
Session 4C: Architecture
- Dipankar Das, Rajeev Kumar, P. P. Chakrabarti:
Dictionary Based Code Compression for Variable Length Instruction Encodings. 545-550 - Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. 551-556 - Andrei Sergeevich Terechko, Manish Garg, Henk Corporaal:
Evaluation of Speed and Area of Clustered VLIW Processors. 557-563 - Nagendran Rangan, Karam S. Chatha:
A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. 564-569 - Kaushal R. Gandhi, Nihar R. Mahapatra:
Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units. 570-575
Session 4D: Power Estimation and Low Power Design
- Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar:
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. 579-585 - Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. 586-591 - Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
Energy-Efficient Compressed Address Transmission. 592-597 - Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Variable Input Delay CMOS Logic for Low Power Design. 598-605 - Ankur Goel, Baquer Mazhari:
Gate Leakage and Its Reduction in Deep Submicron SRAM. 606-611
Session 5A: Interconnect
- Parthasarathi Dasgupta:
Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions. 615-620
- Krishnan Srinivasan, Karam S. Chatha:
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. 623-628 - Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects. 629-633 - Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar:
A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects. 634-639 - Denis Deschacht, Alain Lopez:
Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation. 640-643
Session 5B: Synthesis II
- Madhubanti Mukherjee, Ranga Vemuri:
On Physical-Aware Synthesis of Vertically Integrated 3D Systems. 647-652 - Anup Hosangadi, Farzan Fallah, Ryan Kastner:
Energy Efficient Hardware Synthesis of Polynomial Expressions. 653-658 - C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan:
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores. 659-662 - Renqiu Huang, Ranga Vemuri:
On-Line Synthesis for Partially Reconfigurable FPGAs. 663-668 - Santanu Chattopadhyay, Manas Kumar Dewangan:
A Combinational Logic Mapper for Actel's SX/AX Family. 669-672 - Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas:
A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs. 673-676
Session 5C: Power-Aware Design and Thermal Issues
- Anirudh Devgan, Sani R. Nassif:
Power Variability and Its Impact on Design. 679-682
- Krishnan Sundaresan, Nihar R. Mahapatra:
An Accurate Energy and Thermal Model for Global Signal Buses. 685-690 - Subhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty:
Hot Spots and Zones in a Chip: A Geometrician's View. 691-696 - Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez:
Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. 697-702
Session 5D: Technology
- Srinivas Raghvendra, Philippe Hurat:
DFM: Linking Design and Manufacturing. 705-708 - N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell:
The Impact of Inductance on Transients Affecting Gate Oxide Reliability. 709-713
Session 6A: Test III
- Thara Rejimon, Sanjukta Bhanja:
An Accurate Probalistic Model for Error Detection. 717-722 - Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell:
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. 723-729 - Deepali Koppad, Alexandre V. Bystrov, Alexandre Yakovlev:
Off-Line Testing of Asynchronous Circuits. 730-735 - E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan:
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. 736-741 - Saurabh Goyal, Mihir R. Choudhury, S. S. S. P. Rao, L. Kalyan Kumar:
Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs. 742-747
Session 6B: Algorithms and Applications
- Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan:
A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems. 751-756 - G. N. Nandakumar, Nirav Patel, Raghunatha Reddy, Makeshwar Kothandaraman:
Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models. 757-761 - Hamid Reza Ghasemi, Zainalabedin Navabi:
An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. 762-767 - B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni:
Application of Alpha Power Law Models to PLL Design Methodology. 768-773 - Trevor Pering, Vijay Raghunathan, Roy Want:
Exploiting Radio Hierarchies for Power-Efficient Wireless Device Discovery and Connection Setup. 774-779 - Saurabh Kumar Singh, T. K. Bhattacharyya, Ashudeb Dutta:
Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications. 780-783
Session 6C: Poster Presentations
- Shibaji Banerjee, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury:
Computer Aided Test (CAT) Tool for Mixed Signal SOCs. 787-790 - G. Josemin Bala, J. Raja Paul Perinbam:
A Novel Low Power 16X16 Content Addressable Memory Using PA. 791-794 - Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti:
A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. 795-798 - Nitin Gupta, Doug A. Edwards:
Synthesis of Asynchronous Circuits Using Early Data Validity. 799-803 - Sudarshan Bahukudumbi, Krishna Bharath:
A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores. 804-807 - Sankar P. Debnath, Sukumar Jairam, H. Udayakumar:
A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses. 808-811 - Eduardo Romero, Gabriela Peretti, Carlos A. Marqués:
An Operational Amplifier Model for Test Planning at Behavioral Level. 812-815 - Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan:
Memory-Centric Motion Estimator. 816-819 - Marong Phadoongsidhi, Kewal K. Saluja:
SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits. 820-823 - Yu-Shiang Lin, Dennis Sylvester:
A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction. 824-827 - Mukul Milind Ojha, Arun Kumar Anand, G. S. Visweswaran, D. Nagchoudhuri:
A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip. 828-831 - Murthy Durbhakula:
Applicability of General Purpose Processors to Network Applications. 832-835 - Ramaprasath Vilangudipitchai, Poras T. Balsara:
Power Switch Network Design for MTCMOS. 836-839
Session 6D: Poster Presentations and Research Scholar Forum
- Aditya Sankar Medury, Ingvar Carlson, Atila Alvandpour, John Stensby:
Structural Fault Diagnosis in Charge-Pump Based Phase-Locked Loops. 842-845 - Aliakbar Ghadiri, Hamid Mahmoodi-Meimand:
Dual-Edge Triggered Static Pulsed Flip-Flops. 846-849 - Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee, Sriram Gupta:
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design. 850-853 - Lianxi Liu, Yintang Yang, Zhangming Zhu:
A High Accuracy Bandgap Reference with Chopped Modulator to Compensate MOSFET Mismatch. 854-857 - Biranchinath Sahu, Gabriel A. Rincón-Mora:
A High-Efficiency, Dual-Mode, Dynamic, Buck-Boost Power Supply IC for Portable Applications. 858-861 - Arindam Basu, Anindya Sundar Dhar:
Design Issues in Switched Capacitor Ladder Filters. 862-865 - Shubhajit Roy Chowdhury, C. Pramanik, Hiranmay Saha:
ASIC Design of the Linearisation Circuit of a PTC Thermistor. 866-869 - Tien-Ling Hsieh, Ranjit Gharpurey:
A Reconfigurable Oscillator Topology for Dual-Band Operation. 870-873 - Frank Sill, Frank Grassert, Dirk Timmermann:
Reducing Leakage with Mixed-V_th (MVT). 874-877 - Ghanshyam Nayak, Clyde Washburn, P. R. Mukund:
System in a Package Design of a RF Front End System Using Application Specific Reduced Order Models. 878-881
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