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ORCID12th ReCoSoC 2017: Madrid, Spain
- 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2017, Madrid, Spain, July 12-14, 2017. IEEE 2017, ISBN 978-1-5386-3344-1
- Leandro Soares Indrusiak
, James Harbin, Martha Johanna Sepúlveda:
Side-channel attack resilience through route randomisation in secure real-time Networks-on-Chip. 1-8 - Jan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto García Ortiz, Thilo Pionteck:
Design method for asymmetric 3D interconnect architectures with high level models. 1-8 - Peter Rouget, Benoît Badrignans, Pascal Benoit, Lionel Torres:
SecBoot - lightweight secure boot mechanism for Linux-based embedded systems on FPGAs. 1-5 - Daniela Genius, Ludovic Apvrille:
System-level design for communication-centric task farm applications. 1-8 - Alejandro Nocua, Florent Bruguier, Gilles Sassatelli, Abdoulaye Gamatié:
ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems. 1-8 - Zakarya Guettatfi, Philipp Hübner, Marco Platzner, Bernhard Rinner:
Computational self-awareness as design approach for visual sensor nodes. 1-8 - Antoniette Mondigo, Tomohiro Ueno, Daichi Tanaka, Kentaro Sano, Satoru Yamamoto:
Design and scalability analysis of bandwidth-compressed stream computing with multiple FPGAs. 1-8 - Hamidreza Ahmadian, Farzad Nekouei, Roman Obermaisser:
Fault recovery and adaptation in time-triggered Networks-on-Chips for mixed-criticality systems. 1-8 - Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl:
Towards trace-driven cache attacks on Systems-on-Chips - exploiting bus communication. 1-7 - Leonardo Suriano, Alfonso Rodríguez, Karol Desnos, Maxime Pelcat, Eduardo de la Torre:
Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC. 1-7 - R. Domingo, Rubén Salvador, Himar Fabelo, Daniel Madroñal, Samuel Ortega, Raquel Lazcano, Eduardo Juárez, Gustavo Marrero Callicó, César Sanz:
High-level design using Intel FPGA OpenCL: A hyperspectral imaging spatial-spectral classifier. 1-8 - Marcel Essig, Kurt Franz Ackermann:
On-demand instantiation of co-processors on dynamically reconfigurable FPGAs. 1-8 - Fatemeh Arezoomand, Arghavan Asad, Mahdi Fazeli, Mahmood Fathy, Farah Mohammadi:
Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors. 1-8 - Poona Bahrebar, Dirk Stroobandt:
Adaptive and reconfigurable bubble routing technique for 2D Torus interconnection networks. 1-8 - Stephen Adeboye Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik:
High-level test generation for processing elements in many-core systems. 1-8 - Marta Beltrán, Miguel Calvo, Sergio Gonzalez:
Federated system-to-service authentication and authorization combining PUFs and tokens. 1-8 - Yidi Liu, Monica Villaverde, Félix Moreno, Benjamin Carrión Schäfer:
Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs. 1-8 - Adrián Domínguez, Pedro P. Carballo, Antonio Núñez:
Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm. 1-8 - El Mehdi Abdali, Maxime Pelcat, François Berry, Jean-Philippe Diguet, Francesca Palumbo:
Exploring the performance of partially reconfigurable point-to-point interconnects. 1-6 - Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan:
Fault-resilient NoC router with transparent resource allocation. 1-8 - Piotr Dziurzanski, Tomasz Maka:
Current mode detection in hard real-time automotive applications dedicated to many-core platforms. 1-8
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