default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI 1991: Edinburgh, Scotland
- Arne Halaas, Peter B. Denyer:
VLSI 91, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, Edinburgh, Scotland, 20-22 August, 1991. IFIP Transactions A-1, North-Holland 1992, ISBN 0-444-89019-X
Session 1 Arithmetic
- T. Sato, M. Nakajima, T. Sukemura, G. Goto:
A Regularly Structured 54-bit Modified-Wallace-Tree Multiplier. VLSI 1991: 1-10 - Alain Guyot, Y. Kusumaputri:
OCAPI: A Prototype for High Precision Arithmetic. VLSI 1991: 11-18
Session 2 Digital Signal Processing
- O. C. McNally, John V. McCanny, Roger F. Woods:
Design of a Highly Pipelined 2nd Order IIR Filter Chip. VLSI 1991: 19-28 - Jens Sparsø, Steen Pedersen, Erik Paaske:
Design of a Fully Parallel Viterbi Decoder. VLSI 1991: 29-38 - R. Nagalla, Laurence E. Turner:
Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms. VLSI 1991: 39-48
Session 3a Formal Methods
- Jerry R. Burch, Edmund M. Clarke, David E. Long:
Symbolic Model Checking with Partitioned Transistion Relations. VLSI 1991: 49-58 - Eleanor M. Mayger, Michael P. Fourman:
Integration of Formal Methods with System Design. VLSI 1991: 59-69 - Geraint Jones, Mary Sheeran:
Deriving Bit-Serial Circuits in Ruby. VLSI 1991: 71-80 - Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Structure in Hardware Proofs: First Steps Towards Automation in a Higher-Order Environment. VLSI 1991: 81-90
Session 3b Physical Design
- Konrad Doll, Frank M. Johannes, Georg Sigl:
DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities. VLSI 1991: 91-100 - Stefan Mayrhofer, Massoud Pedram, Ulrich Lauther:
A Flow-Oriented Approach to the Placement of Boolean Networks. VLSI 1991: 101-110 - Habib Youssef, Rung-Bin Lin, Eugene Shragowitz:
Bounds on Net Delays for Physical Design of Fast Circuits. VLSI 1991: 111-118 - Karl-Heinz Erhard, Frank M. Johannes:
Area Minimisation of IC Power/Ground Nets by Topology Optimisation. VLSI 1991: 119-126
Session 4a Simulation
- Herbert Bauer, Christian Sporrer, Thomas H. Krodel:
On Distributed Logic Simulation Using Time Warp. VLSI 1991: 127-136 - Erik Brunvand, M. Starkey:
An Integrated Environment for the Design and Simulation of Self-Timed Systems. VLSI 1991: 137-146 - Tom J. Kazmierski, Andrew D. Brown, Ken G. Nichols, Mark Zwolinski:
A General Purpose Network Solving System. VLSI 1991: 147-156
Session 4b Vision and Neural Architectures
- Peter B. Denyer, David S. Renshaw, Gouyu Wang, Ming Ying Lu, Stuart Anderson:
On-Chip CMOS Sensors for VLSI Imaging Systems. VLSI 1991: 157-166 - J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, Laurent Masse-Navette:
A Customizable Neural Processor for Distributed Neural Network. VLSI 1991: 167-176 - Daniele D. Caviglia, Maurizio Valle, Giacomo M. Bisio:
A VLSI Module for Analog Adaptive Neural Architectures. VLSI 1991: 177-186
Keynote Paper
- A. Richard Newton:
Has CAD for VLSI Reached a Dead End? VLSI 1991: 187-192
Session 5 High Level Synthesis
- Werner Geurts, Stefaan Note, Francky Catthoor, Hugo De Man:
Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications. VLSI 1991: 193-202 - Norbert Wehn, Jörg Biesenack, Michael Pilsl:
A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment. VLSI 1991: 203-213
Session 6a Modelling for Synthesis
- Ahmed Amine Jerraya, Pierre G. Paulin, Simon Curry:
Meta VHDL for Higher Level Controller Modeling and Synthesis. VLSI 1991: 215-224 - Philip A. Wilsey, Timothy J. McBrayer, David Sims:
Towards a Formal Model of VLSI Systems Compativle with VHDL. VLSI 1991: 225-236 - Wolfgang Glunz, Gerd Venzl:
Hardware Design Using CASE Tools. VLSI 1991: 237-246
Session 6b Processor Design
- A. Laudenbach, Manfred Glesner, Norbert Wehn:
A VLSI System Design for the Control of High Performance Combustion Engines. VLSI 1991: 247-256 - Patrice Frison, Dominique Lavenier:
A Fully Integrated Systolic Spelling Co-Processor. VLSI 1991: 257-266 - Wolfram Liebsch, K. Boettcher:
Parallel Architecture and VLSI Implementation of a 80MHz 2D-DCT 80 MHz 2D-DCT/ICDT Processor. VLSI 1991: 267-275
Session 7 RT-Level Synthesis
- Bill Lin, A. Richard Newton:
Exact Redundant State Registers Removal Based on Binary Decision Diagrams. VLSI 1991: 277-286 - P. F. Yeung, D. J. Rees:
Resources Restricted Global Scheduling. VLSI 1991: 287-296 - Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch:
Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays. VLSI 1991: 297-306 - Marina Zanella, Paolo Gubian:
Workspace and Methodology Management in the Octtools Environment. VLSI 1991: 307-316
Session 8a Routing
- Jan Madsen:
Single-Level Wiring for CMOS Functional Cells. VLSI 1991: 317-326 - Ravi R. Pai, S. S. S. P. Rao:
An Over-the-Cell Channel Router. VLSI 1991: 327-336 - M. Starkey, Tony M. Carter:
Switchbox Routing by Pattern Matching. VLSI 1991: 337-346
Session 8b VLSI Arrays
- Donald F. Beal, Costas Lambrinoudakis:
GPFP: A SIMD PE for Higher VLSI Densities. VLSI 1991: 347-356 - Wayne P. Burleson, Louis L. Scharf:
Input/Output Design for VLSI Array Architectures. VLSI 1991: 357-366 - Anders Færgemand Nielsen, Poul Martin Rands Jensen, Kallol Kumar Bagchi, Ole Olsen:
Comparing Transformation Schemes for VLSI Array Processor Design - A Case Study. VLSI 1991: 367-376
Keynote Paper
- Mitsumasa Koyanagi:
A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections. VLSI 1991: 377-386
Session 9 Circuit Design 1
- Farhad Aghdasi:
Pass-Transistor Self-Clocked Asynchronous Sequential Circuits. VLSI 1991: 387-395 - C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III:
Theoretical and Practical Issues in CMOS Wave Pipelining. VLSI 1991: 397-409
Session 10 Circuit Design 2
- Naser Awad, David R. Smith:
Automatic Interfacing of Synchronous Modules to an Asynchronous Environment. VLSI 1991: 411-420 - Bernhard Klaassen:
How to Compare Analog Results. VLSI 1991: 421-428 - Bulent I. Dervisoglu, Gayvin E. Stong:
Application of Scan-Based DFT Methodology for Detecting Static and Timing Failures in VLSI Components. VLSI 1991: 429-438
Session 11 Logic Synthesis and Timing Optimisation
- Sujit Dey, Franc Brglez, Gershon Kedem:
Identification and Resynthesis of Pipelines in Sequential Networks. VLSI 1991: 439-449 - Albert van der Werf, B. T. McSweeney, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh:
Hierarchical Retiming Including Pipelining. VLSI 1991: 451-460 - Ellen Sentovich, Robert K. Brayton:
Preserving Don't Care Conditions During Retiming. VLSI 1991: 461-470
Session 12 Fault Tolerant Arrays
- Manfred Schimmler, Hartmut Schmeck:
A Fault Tolerant and High Speed Instruction Systolic Array. VLSI 1991: 471-480 - Guoning Liao:
A Reconfigurable Fault Tolerant Module Approach to the Reliability Enhancement for Mesh Connected Processor Arrays. VLSI 1991: 481-490 - Ian P. Jalowiecki, Stephen J. Hedge:
The WASP 2 Wafer Scale Integration Demonstrator. VLSI 1991: 491-500
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-31 20:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
