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ORCIDMalgorzata Marek-Sadowska
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- affiliation: University of California, Santa Barbara, USA
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2020 – today
- 2023
[c171]Malgorzata Marek-Sadowska
:
ISPD 2023 Lifetime Achievement Award Bio. ISPD 2023: 265
2010 – 2019
- 2019
- [c170]Ali Abbasinasab, Malgorzata Marek-Sadowska:
Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration. ACM Great Lakes Symposium on VLSI 2019: 117-122 - 2018
- [j71]Ping-Lin Yang, Malgorzata Marek-Sadowska:
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1209-1222 (2018) - [c169]Ali Abbasinasab, Malgorzata Marek-Sadowska:
RAIN: a tool for reliability assessment of interconnect networks - physics to software. DAC 2018: 133:1-133:6 - 2016
- [j70]Zhong Guan, Malgorzata Marek-Sadowska:
Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2195-2207 (2016) - [c168]Ping-Lin Yang, Malgorzata Marek-Sadowska:
Making split-fabrication more secure. ICCAD 2016: 91 - [c167]Zhong Guan, Malgorzata Marek-Sadowska:
An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation. ICCAD 2016: 112 - [c166]Ping-Lin Yang, Malgorzata Marek-Sadowska:
A fast, fully verifiable, and hardware predictable ASIC design methodology. ICCD 2016: 364-367 - [c165]Zhong Guan, Malgorzata Marek-Sadowska:
AFD-based method for signal line EM reliability evaluation. ISQED 2016: 443-449 - 2015
- [j69]Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif:
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 118-130 (2015) - [j68]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly:
Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 869-878 (2015) - [j67]Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif:
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2327-2331 (2015) - [c164]Li-C. Wang, Malgorzata Marek-Sadowska:
Machine Learning in Simulation-Based Analysis. ISPD 2015: 57-64 - [c163]Ali Abbasinasab, Malgorzata Marek-Sadowska:
Blech Effect in Interconnects: Applications and Design Guidelines. ISPD 2015: 111-118 - 2014
- [j66]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study. IEEE Comput. Archit. Lett. 13(2): 81-84 (2014) - [j65]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly:
Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 495-506 (2014) - [c162]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs. DAC 2014: 137:1-137:6 - [c161]Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif:
Statistical analysis of process variation induced SRAM electromigration degradation. ISQED 2014: 700-707 - [c160]Di-An Li, Malgorzata Marek-Sadowska:
Estimating true worst currents for power grid electromigration analysis. ISQED 2014: 708-714 - 2013
- [j64]Xiang Qiu, Malgorzata Marek-Sadowska:
Routing Challenges for Designs With Super High Pin Density. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1357-1368 (2013) - [c159]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly:
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. ISPD 2013: 130-136 - [c158]Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif:
SRAM bit-line electromigration mechanism and its prevention scheme. ISQED 2013: 286-293 - 2012
- [j63]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 266-277 (2012) - [c157]Xiang Qiu, Malgorzata Marek-Sadowska:
Can pin access limit the footprint scaling? DAC 2012: 1100-1106 - [c156]Jen-Yi Wuu, Mark Simmons, Malgorzata Marek-Sadowska:
Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs. ISQED 2012: 193-199 - [c155]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly:
Vertical Slit Field Effect Transistor in ultra-low power applications. ISQED 2012: 384-390 - 2011
- [j62]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 229-241 (2011) - [j61]Aida Todri, Malgorzata Marek-Sadowska:
Reliability Analysis and Optimization of Power-Gated ICs. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 457-468 (2011) - [j60]Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Performance Optimization Using Variable-Latency Design Style. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1874-1883 (2011) - [j59]Aida Todri, Malgorzata Marek-Sadowska:
Power Delivery for Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2243-2255 (2011) - [c154]Jen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska:
Rapid layout pattern classification. ASP-DAC 2011: 781-786 - [c153]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
Layout effects in fine grain 3D integrated regular microprocessor blocks. DAC 2011: 639-644 - [c152]Di-An Li, Malgorzata Marek-Sadowska:
Variation-aware electromigration analysis of power/ground networks. ICCAD 2011: 571-576 - [c151]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
Low power, high throughput network-on-chip fabric for 3D multicore processors. ICCD 2011: 453-454 - [c150]Malgorzata Marek-Sadowska:
On old and new routing problems. ISPD 2011: 13-20 - [c149]Jen-Yi Wuu, Fedor G. Pikus, Malgorzata Marek-Sadowska:
Metrics for characterizing machine learning-based hotspot detection methods. ISQED 2011: 116-121 - 2010
- [j58]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 197-210 (2010) - [c148]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Performance study of VeSFET-based, high-density regular circuits. ISPD 2010: 161-168 - [c147]Vivek S. Nandakumar, David Newmark, Yaping Zhan, Malgorzata Marek-Sadowska:
Statistical static timing analysis flow for transistor level macros in a microprocessor. ISQED 2010: 163-170 - [c146]Di-An Li, Malgorzata Marek-Sadowska, Bill Lee:
On-chip em-sensitive interconnect structures. SLIP 2010: 43-50
2000 – 2009
- 2009
- [j57]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 245-258 (2009) - [j56]Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Spare Cells With Constant Insertion for Engineering Change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 456-460 (2009) - [c145]Aida Todri, Malgorzata Marek-Sadowska:
Electromigration study of power-gated grids. ISLPED 2009: 315-318 - [c144]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Transistor-level layout of high-density regular circuits. ISPD 2009: 83-90 - [c143]Aida Todri, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron:
A study of decoupling capacitor effectiveness in power and ground grid networks. ISQED 2009: 653-658 - 2008
- [j55]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 932-945 (2008) - [c142]Hailin Jiang, Malgorzata Marek-Sadowska:
Power gating scheduling for power/ground noise reduction. DAC 2008: 980-985 - [c141]Aida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya:
Power supply noise aware workload assignment for multi-core systems. ICCAD 2008: 330-337 - [c140]Aida Todri, Malgorzata Marek-Sadowska:
A study of reliability issues in clock distribution networks. ICCD 2008: 101-106 - [c139]Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Timing analysis considering IR drop waveforms in power gating designs. ICCD 2008: 532-537 - [c138]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz:
Is there always performance overhead for regular fabric? ICCD 2008: 557-562 - [c137]Nilesh A. Modi, Malgorzata Marek-Sadowska:
ECO-Map: Technology remapping for post-mask ECO using simulated annealing. ICCD 2008: 652-657 - [c136]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED 2008: 246-253 - 2007
- [j54]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Timing-Aware Power-Noise Reduction in Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 527-541 (2007) - [c135]Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska:
OPC-Free and Minimally Irregular IC Design Style. DAC 2007: 954-957 - [c134]Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. DAC 2007: 976-981 - [c133]Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Engineering change using spare cells with constant insertion. ICCAD 2007: 544-547 - [c132]Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang:
Analysis and optimization of power-gated ICs with multiple power gating configurations. ICCAD 2007: 783-790 - [c131]Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Electromigration and voltage drop aware power grid optimization for power gated ICs. ISLPED 2007: 391-394 - [c130]Hailin Jiang, Malgorzata Marek-Sadowska:
Power-Gating Aware Floorplanning. ISQED 2007: 853-860 - [p2]Bo Hu, Malgorzata Marek-Sadowska:
mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement. Modern Circuit Placement 2007: 229-245 - 2006
- [j53]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Analysis and methodology for multiple-fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 558-575 (2006) - [j52]Qinghua Liu, Malgorzata Marek-Sadowska:
Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 611-624 (2006) - [j51]Yajun Ran, Malgorzata Marek-Sadowska:
Designing via-configurable logic blocks for regular fabric. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 1-14 (2006) - [j50]Yajun Ran, Malgorzata Marek-Sadowska:
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 998-1009 (2006) - [c129]Hailin Jiang, Malgorzata Marek-Sadowska:
Power/ground supply network optimization for power-gating. ICCD 2006: 332-337 - [c128]Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski:
Delay Fault Diagnosis for Non-Robust Test. ISQED 2006: 463-472 - [c127]Chung-Kuan Tsai, Malgorzata Marek-Sadowska:
Analysis of Process Variation's Effect on SRAM's Read Stability. ISQED 2006: 603-610 - [c126]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC 2006: 1-10 - 2005
- [j49]Kai Wang, Malgorzata Marek-Sadowska:
On-chip power-supply network optimization using multigrid-based technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 407-417 (2005) - [j48]Qinghua Liu, Malgorzata Marek-Sadowska:
A study of netlist structure and placement efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 762-772 (2005) - [j47]Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska:
General skew constrained clock network sizing based on sequential linear programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 773-782 (2005) - [j46]Bo Hu, Malgorzata Marek-Sadowska:
Multilevel fixed-point-addition-based VLSI placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1188-1203 (2005) - [j45]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Delay-fault diagnosis using timing information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1315-1325 (2005) - [j44]Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Eliminating false positives in crosstalk noise analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1406-1419 (2005) - [c125]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Skew-programmable clock design for FPGA and skew-aware placement. FPGA 2005: 33-40 - [c124]Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska:
Clock skew bounds estimation under power supply and process variations. ACM Great Lakes Symposium on VLSI 2005: 332-336 - [c123]Qinghua Liu, Malgorzata Marek-Sadowska:
A congestion-driven placement framework with local congestion prediction. ACM Great Lakes Symposium on VLSI 2005: 488-493 - [c122]Yajun Ran, Malgorzata Marek-Sadowska:
Via-configurable routing architectures and fast design mappability estimation for regular fabrics. ICCAD 2005: 25-32 - [c121]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Timing-aware power noise reduction in layout. ICCAD 2005: 627-634 - [c120]Qinghua Liu, Malgorzata Marek-Sadowska:
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. ICCD 2005: 31-37 - [c119]Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif:
Benefits and Costs of Power-Gating Technique. ICCD 2005: 559-566 - [c118]Qinghua Liu, Malgorzata Marek-Sadowska:
Wire length prediction-based technology mapping and fanout optimization. ISPD 2005: 145-151 - [c117]Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska:
mFAR: fixed-points-addition-based VLSI placement algorithm. ISPD 2005: 239-241 - [c116]Chung-Kuan Tsai, Malgorzata Marek-Sadowska:
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. ISQED 2005: 654-661 - 2004
- [j43]Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska:
Pipelining Sequential Circuits with Wave Steering. IEEE Trans. Computers 53(9): 1205-1210 (2004) - [j42]Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen:
Fast postplacement optimization using functional symmetries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 102-118 (2004) - [j41]Bo Hu, Malgorzata Marek-Sadowska:
Fine granularity clustering-based placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 527-536 (2004) - [j40]Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska:
Individual wire-length prediction with application to timing-driven placement. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1004-1014 (2004) - [j39]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1028-1037 (2004) - [c115]Yajun Ran, Malgorzata Marek-Sadowska:
Designing a via-configurable regular fabric. CICC 2004: 423-426 - [c114]Kai Wang, Malgorzata Marek-Sadowska:
Buffer sizing for clock power minimization subject to general skew constraints. DAC 2004: 159-164 - [c113]Yajun Ran, Malgorzata Marek-Sadowska:
On designing via-configurable cell blocks for regular fabrics. DAC 2004: 198-203 - [c112]Qinghua Liu, Malgorzata Marek-Sadowska:
Pre-layout wire length and congestion estimation. DAC 2004: 582-587 - [c111]Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Eliminating False Positives in Crosstalk Noise Analysis. DATE 2004: 1192-1197 - [c110]Bo Hu, Malgorzata Marek-Sadowska:
Multilevel expansion-based VLSI placement with blockages. ICCAD 2004: 558-564 - [c109]Yajun Ran, Malgorzata Marek-Sadowska:
An integrated design flow for a via-configurable gate array. ICCAD 2004: 582-589 - [c108]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Diagnosis of Hold Time Defects. ICCD 2004: 192-199 - [c107]Kai Wang, Malgorzata Marek-Sadowska:
Potential Slack Budgeting with Clock Skew Optimization. ICCD 2004: 265-271 - [c106]Yajun Ran, Malgorzata Marek-Sadowska:
The Magic of a Via-Configurable Regular Fabric. ICCD 2004: 338-343 - [c105]Kai Wang, Malgorzata Marek-Sadowska:
Clock network sizing via sequential linear programming with time-domain analysis. ISPD 2004: 182-189 - [c104]Qinghua Liu, Malgorzata Marek-Sadowska:
A study of netlist structure and placement efficiency. ISPD 2004: 198-203 - [c103]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Delay Fault Diagnosis Using Timing Information. ISQED 2004: 485-490 - 2003
- [j38]Arindam Mukherjee, Malgorzata Marek-Sadowska:
Clock and Power Gating with Timing Closure. IEEE Des. Test Comput. 20(3): 32-39 (2003) - [j37]Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska:
A new reasoning scheme for efficient redundancy addition and removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 945-951 (2003) - [j36]Arindam Mukherjee, Malgorzata Marek-Sadowska:
Wave steering to integrate logic and physical syntheses. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 105-120 (2003) - [j35]Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska:
PITIA: an FPGA for throughput-intensive applications. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 354-363 (2003) - [j34]Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer:
Buffer delay change in the presence of power and ground noise. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 461-473 (2003) - [c102]Kai Wang, Malgorzata Marek-Sadowska:
On-chip power supply network optimization using multigrid-based technique. DAC 2003: 113-118 - [c101]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Delay budgeting in sequential circuit with application on FPGA placement. DAC 2003: 202-207 - [c100]Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska:
Gain-based technology mapping for discrete-size cell libraries. DAC 2003: 574-579 - [c99]Bo Hu, Malgorzata Marek-Sadowska:
Wire length prediction based clustering and its application in placement. DAC 2003: 800-805 - [c98]Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Temporofunctional crosstalk noise analysis. DAC 2003: 860-863 - [c97]Yajun Ran, Malgorzata Marek-Sadowska:
Crosstalk noise in FPGAs. DAC 2003: 944-949 - [c96]Kai Wang, Malgorzata Marek-Sadowska:
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. DATE 2003: 10850-10855 - [c95]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Minimum-Area Sequential Budgeting for FPGA. ICCAD 2003: 813-817 - [c94]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Multiple Fault Diagnosis Using n-Detection Tests. ICCD 2003: 198- - [c93]Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
A crosstalk aware two-pin net router. ISCAS (5) 2003: 485-488 - [c92]Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
Minimizing coupling jitter by buffer resizing for coupled clock networks. ISCAS (5) 2003: 509-512 - [c91]