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ORCIDVLSI Design, Volume 7
Volume 7, Number 1, 1998
- Jun-Dong Cho:
Guest Editorial. - Dimitrios Karayiannis, Spyros Tragoudas:
Clustering Network Modules with Different Implementations for Delay Minimization. 1-13 - Gustavo E. Téllez, Majid Sarrafzadeh:
On Rectilinear Distance-Preserving Trees. 15-30 - José Luis Neves, Eby G. Friedman:
Automated Synthesis of Skew-Based Clock Distribution Networks. 31-57 - Ashok Vittal, Malgorzata Marek-Sadowska:
Power Distribution Synthesis for VLSI. 59-72 - Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
:
Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. 73-84 - Kyoung-Son Jhang, Soonhoi Ha, Chu Shik Jhon:
Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing. 85-95 - Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins:
Placement and Routing for Performance-Oriented FPGA Layout. 97-110 - André DeHon, Thomas F. Knight Jr.:
High Performance, Point-to-Point, Transmission Line Signaling. 111-129
Volume 7, Number 2, 1998
- C. P. Ravikumar, Hemant Joshi:
SCOAP-based Testability Analysis from Hierarchical Netlists. 131-141 - Vincenzo Acciaro, Amiya Nayak:
Characterization of Catastrophic Faults in Reconfigurable Systolic Arrays. 143-150 - Fadi Busaba, Parag K. Lala, Alvernon Walker:
On Self-Checking Design of CMOS Circuits for Multiple Faults. 151-161 - Gerald Spiegel, Albrecht P. Stroele:
Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults. 163-176 - Ioannis Karafyllidis, Ioannis Andreadis, Philippos G. Tsalides, Adonios Thanailakis:
Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems. 177-189 - Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak:
Syndrome Signature in Output Compaction for VLSI Built-in Self-Test. 191-201 - Ioannis Andreadis, I. Kokolakis, Antonios Gasteratos, Philippos G. Tsalides:
A Stochastic D/A Converter Based on a Cellular Automaton Architecture. 203-210 - Dimitrios Karayiannis, Spyros Tragoudas:
Timing-Driven Circuit Implementation. 211-224
Volume 7, Number 3, 1998
- Farid N. Najm, Gary Yeap:
Guest Editorial. - Vivek Tiwari, Mike Tien-Chien Lee:
Power Analysis of a 32-bit Embedded Microcontroller. 225-242 - Farid N. Najm, Michael G. Xakellis:
Statistical Estimation of the , Switching Activity in VLSI Circuits. 243-254 - Srinivas Katkoori, Ranga Vemuri:
Architectural Power Estimation Based on Behavior Level Profiling. 255-270 - Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh:
Exploiting Sleep Mode for Memory Partitioning and Other Applications. 271-287 - Rajendran Panda, Farid N. Najm:
Post-Mapping Transformations for Low-Power Synthesis. 289-301 - Catherine H. Gebotys:
Optimizing Energy During Systems Synthesis of Computer Intensive Realtime Applications. 303-320
Volume 7, Number 4, 1998
- François Verdier, Bertrand Y. Zavidovique:
A High Level Synthesis System for VLSI Image Processing Applications. 321-336 - Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose:
Complexity of Scheduling in High Level Synthesis. 337-346 - C. P. Ravikumar, Nikhil Sharma:
Testability-Driven Layout of Combinational Circuits. 347-352 - Sudip Nag, Kaushik Roy:
Performance and Wirability Driven Layout for Row-Based FPGAs. 353-364 - Teofilo F. Gonzalez, Si-Qing Zheng:
On Ensuring Multilayer Wirability by Stretching Layouts. 365-383 - Ray-I Chang, Pei-Yung Hsiao:
Macro-Cell Placement for Custom-Chip Design Using Self-Organizing Fuzzy Technique. 385-399 - Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni:
Formal Codesign Methodology with Multistep Partitioning. 401-423 - Dinesh P. Mehta:
CLOTH MEASURE: A Software Tool for Estimating the Memory Requirements of Corner Stitching Data Structures. 425-436
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