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ORCID3. Great Lakes Symposium on VLSI 1993: Kalamazoo, MI, USA
- Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, Kalamazoo, MI, USA, March 5-6, 1993. IEEE 1993, ISBN 0-8186-3430-8
- Ronald I. Greenberg, Jau-Der Shih:
Minimizing channel density with movable terminals. 1-5 - Timothy W. Strunk, Nancy D. Holmes:
VICTOR: A three-layer over-the-cell router. 6-10 - Antonije D. Jovanovic:
Modeling the vertical constraints in VLSI channel routing. 11-13 - Enrico Macii, Qing Xu:
Modeling stuck-open faults in CMOS iterative circuits. 14-17 - Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
Delay fault testability evaluation through timing simulation. 18-21 - Nikrouz Faroughi:
C-testable systolic arrays. 22-26 - Young-Chul Kim, Michael A. Shanblatt:
A VLSI-based digital multilayer neural network architecture. 27-31 - Paul Mukai, Mark Busa, Peter T. Kazlas:
Neural system design with the integrated neurocomputing architecture. 32-36 - V. Upadhyaya, Shambhu J. Upadhyaya, Amlan Kundu:
A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition. 37-41 - Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal:
Clock partitioning for testability. 42-46 - Stephen J. Muscato, Alexander Albicki:
Locally clocked microprocessor. 47-51 - Slobodan Simovich, Paul D. Franzon, Michael B. Steer:
A simple method for noise tolerance characterization of digital circuits. 52-56 - Jon Hamkins, Donna J. Brown:
Switchbox routing with movable terminals. 57-61 - Jeffrey S. Salowe, Dana S. Richards, Dallas E. Wrege:
Mixed spanning trees: a technique for performance-driven routing. 62-66 - George Blust, Dinesh P. Mehta
:
Corner stitching for L-shaped tiles. 67-68 - B. B. Prahlada Rao, Lalit M. Patnaik, R. C. Hansdah:
Parallel genetic algorithm for channel routing. 69-70 - S. Aranake, Vijay K. Raj, M. Vashi, Hee Yong Youn:
Optimal register allocation in high level synthesis. 71-75 - Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Efficient minimization algorithms for fixed polarity AND/XOR canonical networks. 76-79 - Liang-Fang Chao, Edwin Hsing-Mean Sha:
Rate-optimal static scheduling for DSP data-flow programs. 80-84 - Richard Auletta, Cherrice Traver:
Rapid-prototyping of high-assurance systems. 85-89 - Tim Barrera, Jeff Griffith, Sally A. McKee, Gabriel Robins, Tongtong Zhang:
Toward a Steiner engine: enhanced serial and parallel implementations of the iterated 1-Steiner MRST algorithm. 90-94 - S. C. Gadre, Ramachandran Vaidyanathan, Si-Qing Zheng:
A potential-driven approach to constructing rectilinear Steiner trees. 95-99 - Spyros Tragoudas:
Minmax-cut graph partitioning problems. 100-104 - Forbes D. Lewis, Wang Chia-Chi Pong, Nancy K. Van Cleave:
Local improvement in Steiner trees. 105-106 - Jason K. Davis, Enrico Macii:
Δ-trees of a graph: introduction and formal definition. 107-108 - Gary W. Panzer:
Automating the packaging selection of VLSI systems. 109-113 - Avinash C. Palaniswamy, Philip A. Wilsey:
Adaptive bounded time windows in an optimistically synchronized simulator. 114-118 - Clark D. Thomborson, Yi Sun:
Optimizing carry lookahead adders for semicustom CMOS. 119-122 - Yulin Chen, Wei Kang Tsai, Fadi J. Kurdahi:
A logic synthesis system based on global dynamic extraction and flexible cost. 123-126 - Subra Ganesan, S. Mahalingam, S. Nagabhushana:
VLSI synthesis of a programmable DWT chip for the optimal choice of a prototype wavelet. 127-131 - Thomas Charles Wilson, Manoj K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji:
MinMux: a new approach for global minimization of multiplexers in interconnect synthesis. 132-138 - Tam Anh Chu, Narayana Mani, Clement K. C. Leung:
A new state assignment technique for asynchronous finite state machines. 139-143
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