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ORCIDHLDVT 2009: San Francisco, CA, USA
- IEEE International High Level Design Validation and Test Workshop, HLDVT 2009, San Francisco, CA, USA, 4-6 November 2009. IEEE Computer Society 2009, ISBN 978-1-4244-4823-4
- Priyank Kalla, Prabhat Mishra
:
Chairs' welcome message. 1 - Sunil R. Shenoy:
Leadership Microprocessors: Validation, debug and test. 1 - Bin Xue, Sandeep K. Shukla:
Analysis of scheduled Latency insensitive systems with periodic clock calculus. 1-7 - Miroslav N. Velev, Ping Gao:
Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality. 8-13 - Maurizio Caramia, Stefano Di Carlo, Michele Fabiano, Paolo Prinetto:
FLARE: A design environment for FLASH-based space applications. 14-19 - Sumit Ahuja, Sandeep K. Shukla:
MCBCG: Model Checking Based Sequential Clock-Gating. 20-25 - Sean Safarpour, Andreas G. Veneris:
Automated debugging with high level abstraction and refinement. 26-31 - Lingyi Liu, Shobha Vasudevan:
STAR: Generating input vectors for design validation by static analysis of RTL. 32-37 - In-Ho Moon, Kevin Harer:
Learning from constraints for formal property checking. 38-45 - Gianpiero Cabodi, Leandro Dipietro, Marco Murciano, Sergio Nocco:
Exploiting incrementality in SAT-based search for multiple equivalence-preserving transformations in combinational circuits. 46-53 - J. Hao, Valeria Bertacco:
PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis. 54-59 - Kanupriya Gulati, Sunil P. Khatri:
Fault table generation using Graphics Processing Units. 60-67 - Maheshwar Chandrasekar, Michael S. Hsiao:
Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility. 68-75 - Huan Chen, João Marques-Silva:
TG-PRO: A new model for SAT-based ATPG. 76-81 - Susmit Jha, Wenchao Li, Sanjit A. Seshia:
Localizing transient faults using dynamic bayesian networks. 82-87 - Peter Lisherness, Kwang-Ting Cheng:
An instrumented observability coverage method for system validation. 88-93 - Ziyad Hanna, Thomas F. Melham:
A symbolic execution framework for algorithm-level modelling. 94-99 - Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer:
Dynamic verification of Multicore Communication applications in MCAPI. 100-105 - Jason G. Tong, Marc Boule, Zeljko Zilic:
Airwolf-TG: A test generator for assertion-based dynamic verification. 106-113 - Yongquan Fan, Zeljko Zilic:
A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces. 114-121 - Sven Verdoolaege, Martin Palkovic, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor:
Experience with widening based equivalence checking in realistic multimedia systems. 122-129 - Hao Zheng:
A coordinated reachability analysis method for modular verification of asynchronous designs. 130-137 - Bijan Alizadeh, Masahiro Fujita:
Modular arithmetic decision procedure with auto-correction mechanism. 138-145 - Debapriya Chatterjee, Valeria Bertacco:
Activity-based refinement for abstraction-guided simulation. 146-153 - Sung-Boem Park, Subhasish Mitra:
IFRA: Post-silicon bug localization in processors. 154-159 - Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara:
RTL DFT techniques to enhance defect coverage for functional test sequences. 160-165 - Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia:
Hardware Trojan: Threats and emerging solutions. 166-171 - Nicola Nicolici, Ho Fai Ko:
Design-for-debug for post-silicon validation: Can high-level descriptions help? 172-175
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