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2010 – 2019
- 2011
[j3]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
Two-Stage, Pipelined Register Renaming. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1926-1931 (2011)- 2010
- [j2]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 365-377 (2010)
2000 – 2009
- 2009
- [c7]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. ICSAMOS 2009: 41-48 - 2008
- [j1]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 628-638 (2008) - [c6]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
A physical level study and optimization of CAM-based checkpointed register alias table. ISLPED 2008: 233-236 - 2007
- [c5]Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni:
On the latency, energy and area of checkpointed, superscalar register alias tables. ISLPED 2007: 379-382 - [c4]Jason Zebchuk, Elham Safi, Andreas Moshovos:
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. MICRO 2007: 314-327 - 2006
- [c3]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
L-CBF: a low-power, fast counting bloom filter architecture. ISLPED 2006: 250-255 - 2003
- [c2]Elham Safi, Zohreh Karimi, Maghsoud Abbaspour
, Zainalabedin Navabi:
Utilizing Various ADL Facets for Instruction Level CPU Test. MTV 2003: 38- - [c1]Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi:
Processor Testing Using an ADL Description and Genetic Algorithms. VLSI-SOC 2003: 186-
Coauthor Index
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