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ORCIDQiang Zhou 0001
Person information
- affiliation: Tsinghua University, Department of Computer Science and Technology, Beijing, China
- affiliation (PhD 2002): Chinese University of Mining and Technology, Beijing, China
Other persons with the same name
- Qiang Zhou — disambiguation page
- Qiang Zhou 0002
![[0000-0003-1348-8861]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-1348-8861")
— University of Arizona, Tucson, AZ, USA (and 2 more) - Qiang Zhou 0003 — The Ohio State University, Department of Chemical and Biomolecular Engineering, Columbus, OH, USA (and 1 more)
- Qiang Zhou 0004 — Chongqing University, State Key Laboratory of Mechanical Transmission, China
- Qiang Zhou 0005 — Tsinghua University, Research Institute of Information Technology, TNList, Beijing, China
- Qiang Zhou 0006 — Hong Kong Shue Yan University, Department of Accounting (and 1 more)
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Journal Articles
- 2023
[j50]Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu:
McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 243-256 (2023)- 2022
- [j49]Rui Hao, Yici Cai, Qiang Zhou:
Intelligent and kernelized placement: A survey. Integr. 86: 44-50 (2022) - [j48]Lin Li, Yici Cai, Qiang Zhou:
A survey on machine learning-based routing for VLSI physical design. Integr. 86: 51-56 (2022) - 2021
- [j47]Haoyi Wang, Yici Cai, Qiang Zhou:
A game theory approach for RTL security verification resources allocation. CCF Trans. High Perform. Comput. 3(1): 57-69 (2021) - [j46]Jing Wang, Yici Cai, Qiang Zhou:
Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks. J. Comput. Sci. Technol. 36(5): 1133-1144 (2021) - [j45]Jianwang Zhai, Yici Cai, Qiang Zhou:
Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1571-1575 (2021) - 2019
- [j44]Wenyan Wu, Xingzhe Wu, Yici Cai, Qiang Zhou:
Deep coupling neural network for robust facial landmark detection. Comput. Graph. 82: 286-294 (2019) - [j43]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding. Integr. 67: 108-120 (2019) - [j42]Haoyi Wang, Chenguang Wang, Yici Cai, Qiang Zhou:
A high-level information flow tracking method for detecting information leakage. Integr. 69: 393-399 (2019) - [j41]Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao:
Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 57-69 (2019) - [j40]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1844-1857 (2019) - 2018
- [j39]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
Spear and Shield: Evolution of Integrated Circuit Camouflaging. J. Comput. Sci. Technol. 33(1): 42-57 (2018) - [j38]Shan Jiang, Ning Xu, Xueyan Wang, Qiang Zhou:
An Efficient Technique to Reverse Engineer Minterm Protection Based Camouflaged Circuit. J. Comput. Sci. Technol. 33(5): 998-1006 (2018) - [j37]Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu:
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 217-230 (2018) - 2016
- [j36]Jiliang Zhang, Qiang Wu, Yipeng Ding, Yong-Qiang Lv, Qiang Zhou, Zhihua Xia, Xingming Sun, Xing-Wei Wang:
Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function. J. Comput. Sci. Technol. 31(1): 124-136 (2016) - 2015
- [j35]Hailong Yao, Fan Yang, Yici Cai, Qiang Zhou, Chiu-Wing Sham:
SIAR: Customized real-time interactive router for analog circuits. Integr. 48: 170-182 (2015) - [j34]Chao Deng, Yici Cai, Qiang Zhou:
Register Clustering Methodology for Low Power Clock Tree Synthesis. J. Comput. Sci. Technol. 30(2): 391-403 (2015) - [j33]Zhongdong Qi, Yici Cai, Qiang Zhou:
Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths. J. Comput. Sci. Technol. 30(3): 614-628 (2015) - [j32]Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze:
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 142-155 (2015) - [j31]Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao:
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2617-2628 (2015) - 2014
- [j30]Jiliang Zhang, Gang Qu, Yong-Qiang Lv, Qiang Zhou:
A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs. J. Comput. Sci. Technol. 29(4): 664-678 (2014) - [j29]Yong-Qiang Lv, Qiang Zhou, Yici Cai, Gang Qu:
Trusted Integrated Circuits: The Problem and Challenges. J. Comput. Sci. Technol. 29(5): 918-928 (2014) - [j28]Hailong Yao, Qiang Gao, Yici Cai, Qiang Zhou, Chiu-Wing Sham:
Length matching in detailed routing for analog and mixed signal circuits. Microelectron. J. 45(6): 604-612 (2014) - [j27]Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi:
Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 899-912 (2014) - [j26]Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush: An Efficient Simulator for Static Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2103-2116 (2014) - 2013
- [j25]Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang:
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. Integr. 46(1): 1-9 (2013) - 2012
- [j24]Jiliang Zhang, Yongqiang Lu, Qiang Zhou, Qiang Wu, Yaping Lin, Kang Zhao:
TimFastPlace: Critical-path based timing driven FastPlace. IEICE Electron. Express 9(16): 1310-1315 (2012) - 2011
- [j23]Qiang Zhou, Jin Shi, Bin Liu, Yici Cai:
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 638-646 (2011) - 2010
- [j22]Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong:
Thermal Impacts of Leakage Power in 2D/3D floorplanning. J. Circuits Syst. Comput. 19(7): 1483-1495 (2010) - [j21]Hui Dai, Qiang Zhou, Jinian Bian:
Multilevel Optimization for Large-Scale Hierarchical FPGA Placement. J. Comput. Sci. Technol. 25(5): 1083-1091 (2010) - [j20]Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong:
ECP- and CMP-Aware Detailed Routing Algorithm for DFM. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 153-157 (2010) - 2009
- [j19]Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian:
Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3151-3159 (2009) - [j18]Haixia Yan, Qiang Zhou, Xianlong Hong:
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach. Integr. 42(2): 175-180 (2009) - [j17]Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong:
An MTCMOS technology for low-power physical design. Integr. 42(3): 340-345 (2009) - 2008
- [j16]Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang:
Application of optical proximity correction technology. Sci. China Ser. F Inf. Sci. 51(2): 213-224 (2008) - [j15]Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong:
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(8): 2084-2090 (2008) - 2007
- [j14]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
Voltage Island Generation in Cell Based Dual-Vdd Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 267-273 (2007) - [j13]Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu:
An efficient quadratic placement based on search space traversing technology. Integr. 40(3): 253-260 (2007) - [j12]Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong:
A Yield-Driven Gridless Router. J. Comput. Sci. Technol. 22(5): 653-660 (2007) - [j11]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 645-658 (2007) - 2006
- [j10]Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong:
Priority-Based Routing Resource Assignment Considering Crosstalk. J. Comput. Sci. Technol. 21(6): 913-921 (2006) - [j9]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1007-1011 (2006) - [j8]Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong:
Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1148-1152 (2006) - [j7]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2637-2646 (2006) - [j6]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani:
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006) - 2005
- [j5]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Crosstalk and Congestion Driven Layer Assignment Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(6): 1565-1572 (2005) - [j4]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan:
A Fast Delay Computation for the Hybrid Structured Clock Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(7): 1964-1970 (2005) - [j3]Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3405-3411 (2005) - [j2]Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong:
Crosstalk-Aware Routing Resource Assignment. J. Comput. Sci. Technol. 20(2): 231-236 (2005) - [j1]Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong:
Shielding Area Optimization Under the Solution of Interconnect Crosstalk. J. Comput. Sci. Technol. 20(6): 901-906 (2005)
Conference and Workshop Papers
- 2023
- [c112]Haoyi Wang, Qiang Zhou, Yici Cai:
Static Probability Analysis Guided RTL Hardware Trojan Test Generation. ASP-DAC 2023: 510-515 - 2022
- [c111]Shiling Luo, Wenchao Gao, Le Huang, Qiang Zhou:
A circuit protection method based on minterm perturbation. CIS 2022: 360-365 - [c110]Wenyan Wu, Yici Cai, Qiang Zhou:
TransMarker: A Pure Vision Transformer for Facial Landmark Detection. ICPR 2022: 3580-3587 - 2021
- [c109]Qiang Zhou, Chaohui Yu, Zhibin Wang, Qi Qian, Hao Li:
Instant-Teaching: An End-to-End Semi-Supervised Object Detection Framework. CVPR 2021: 4081-4090 - [c108]Wenyan Wu, Yici Cai, Qiang Zhou:
SRL: Separation-and-Recombination Learning for Video Facial Landmark Detection with Limited Data. FG 2021: 1-8 - [c107]Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu:
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. ICCAD 2021: 1-9 - [c106]Qiang Zhou, Wei Chen, Weiqing Wang, Jiajie Xu, Lei Zhao:
Multiple Features Driven Author Name Disambiguation. ICWS 2021: 506-515 - [c105]Lin Li, Yici Cai, Qiang Zhou:
An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network. ISCAS 2021: 1-5 - [c104]Jing Wang, Yici Cai, Qiang Zhou:
A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model. ISCAS 2021: 1-5 - 2020
- [c103]Zhuoqian Yang, Wentao Zhu, Wayne Wu, Chen Qian, Qiang Zhou, Bolei Zhou, Chen Change Loy:
TransMoMo: Invariance-Driven Unsupervised Video Motion Retargeting. CVPR 2020: 5305-5314 - 2019
- [c102]Keqiang Sun, Wayne Wu, Tinghao Liu, Shuo Yang, Quan Wang, Qiang Zhou, Zuochang Ye, Chen Qian:
FAB: A Robust Facial Landmark Detection Framework for Motion-Blurred Videos. ICCV 2019: 5461-5470 - [c101]Jing Wang, Yici Cai, Ming Yan, Qiang Zhou:
Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks. ISCAS 2019: 1-5 - 2018
- [c100]Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang:
ASAX: Automatic security assertion extraction for detecting Hardware Trojans. ASP-DAC 2018: 84-89 - [c99]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
A conflict-free approach for parallelizing SAT-based de-camouflaging attacks. ASP-DAC 2018: 259-264 - [c98]Chenguang Wang, Yici Cai, Qiang Zhou:
HLIFT: A high-level information flow tracking method for detecting hardware Trojans. ASP-DAC 2018: 727-732 - [c97]Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou:
Look at Boundary: A Boundary-Aware Face Alignment Algorithm. CVPR 2018: 2129-2138 - [c96]Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou:
Electromigration Design Rule aware Global and Detailed Routing Algorithm. ACM Great Lakes Symposium on VLSI 2018: 267-272 - [c95]Chenguang Wang, Yici Cai, Haoyi Wang, Qiang Zhou:
Electromagnetic equalizer: an active countermeasure against EM side-channel attack. ICCAD 2018: 112 - [c94]Jia Wei, Qiang Zhou, Yici Cai:
Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks. ICNC 2018: 156-160 - 2017
- [c93]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack. ACM Great Lakes Symposium on VLSI 2017: 345-350 - [c92]Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang:
Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. ICCD 2017: 305-312 - [c91]Chenguang Wang, Yici Cai, Qiang Zhou:
Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans. ICCD 2017: 321-328 - [c90]Xueyan Wang, Yici Cai, Qiang Zhou:
Cell spreading optimization for force-directed global placers. ISCAS 2017: 1-4 - [c89]Zihan Pang, Jiliang Zhang, Qiang Zhou, Shuqian Gong, Xu Qian, Bin Tang:
Crossover Ring Oscillator PUF. ISQED 2017: 237-243 - [c88]Ming Yan, Yici Cai, Chenguang Wang, Qiang Zhou:
An Effective Power Grid Optimization Approach for the Electromigration Reliability. ISVLSI 2017: 453-458 - 2016
- [c87]Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu:
MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router. ACM Great Lakes Symposium on VLSI 2016: 87-92 - [c86]Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu:
Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. ACM Great Lakes Symposium on VLSI 2016: 133-136 - [c85]Zhuwei Chen, Yici Cai, Qiang Zhou, Gang Qu:
An efficient framework for configurable RO PUF. ISCAS 2016: 742-745 - [c84]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
Is the Secure IC camouflaging really secure? ISCAS 2016: 1710-1713 - 2015
- [c83]Mingze Gao, Khai Lai, Jiliang Zhang, Gang Qu, Aijiao Cui, Qiang Zhou:
Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators. CAD/Graphics 2015: 194-201 - [c82]Chao Deng, Yici Cai, Qiang Zhou:
Fast synthesis of low power clock trees based on register clustering. ISQED 2015: 303-309 - 2014
- [c81]Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen:
VFGR: A very fast parallel global router with accurate congestion modeling. ASP-DAC 2014: 525-530 - [c80]Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou:
Power supply noise aware evaluation framework for side channel attacks and countermeasures. FPT 2014: 161-166 - [c79]Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li:
MCFRoute: a detailed router based on multi-commodity flow method. ICCAD 2014: 397-404 - [c78]Zhongdong Qi, Yici Cai, Qiang Zhou:
Accurate prediction of detailed routing congestion using supervised data learning. ICCD 2014: 97-103 - [c77]Chao Deng, Yici Cai, Qiang Zhou:
A register clustering algorithm for low power clock tree synthesis. ISCAS 2014: 389-392 - [c76]Ziyang Qi, Kun Ma, Qiang Zhou, Yici Cai:
RSMT construction algorithm based on Congestion-Oriented Flexibility. LASCAS 2014: 1-4 - 2013
- [c75]Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou:
Analog routing considering min-area constraint. ASICON 2013: 1-4 - [c74]Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou:
A new splitting graph construction algorithm for SIAR router. ASICON 2013: 1-4 - [c73]Zhongdong Qi, Yici Cai, Qiang Zhou:
Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model. CAD/Graphics 2013: 74-80 - [c72]Jiliang Zhang, Qiang Wu, Yongqiang Lyu, Qiang Zhou, Yici Cai, Yaping Lin, Gang Qu:
Design and Implementation of a Delay-Based PUF for FPGA IP Protection. CAD/Graphics 2013: 107-114 - [c71]Chi-En Daniel Yin, Gang Qu, Qiang Zhou:
Design and implementation of a group-based RO PUF. DATE 2013: 416-421 - [c70]Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian:
Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits. FCCM 2013: 227 - [c69]Jiliang Zhang, Yaping Lin, Yongqiang Lyu, Gang Qu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian:
FPGA IP protection by binding Finite State Machine to Physical Unclonable Function. FPL 2013: 1-4 - [c68]Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao:
Selected inversion for vectorless power grid verification by exploiting locality. ICCD 2013: 257-263 - 2012
- [c67]Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie:
Thermal-aware power network design for IR drop reduction in 3D ICs. ASP-DAC 2012: 47-52 - [c66]Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush : Efficient transient simulation for power grid analysis. ICCAD 2012: 653-659 - [c65]Wenchao Gao, Qiang Zhou, Xu Qian, Yici Cai:
A DyadicCluster method used for nonlinear placement. ISQED 2012: 418-423 - 2011
- [c64]Liu Liu, Yongqiang Lu, Qiang Zhou:
A timing-perspective study on the wire model in placement. ASICON 2011: 910-913 - [c63]Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai:
A fast recursive detailed routing algorithm for hierarchical FPGAs. CSCWD 2011: 91-96 - [c62]Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze:
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI 2011: 199-204 - [c61]Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai:
SIAR: splitting-graph-based interactive analog router. ACM Great Lakes Symposium on VLSI 2011: 367-370 - [c60]Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush: A linear simulator for power grid. ICCAD 2011: 482-487 - [c59]Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi:
Fast poisson solver preconditioned method for robust power grid analysis. ICCAD 2011: 531-536 - [c58]Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai:
A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. ISQED 2011: 36-41 - [c57]Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao:
A novel fine-grain track routing approach for routability and crosstalk optimization. ISQED 2011: 621-626 - [c56]Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai:
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. ISVLSI 2011: 212-217 - 2010
- [c55]Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian:
An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. CSCWD 2010: 701-706 - [c54]Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian:
Behavioral level dual-vth design for reduced leakage power with thermal awareness. DATE 2010: 1261-1266 - [c53]Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu:
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. DATE 2010: 1369-1372 - [c52]Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou:
Peak current reduction by simultaneous state replication and re-encoding. ICCAD 2010: 592-595 - [c51]Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu:
Useful clock skew optimization under a multi-corner multi-mode design framework. ISQED 2010: 62-68 - [c50]Dawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian:
A low power clock network placement framework. ISQED 2010: 771-776 - 2009
- [c49]Junbo Yu, Qiang Zhou, Jinian Bian:
Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. ASP-DAC 2009: 85-90 - [c48]Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong:
Fast placement for large-scale hierarchical FPGAs. CAD/Graphics 2009: 190-194 - [c47]Dawei Liu, Qiang Zhou, Jinian Bian, Yanming Jia:
Global density smoothing technique for analytical placement algorithm. CAD/Graphics 2009: 389-393 - [c46]Yun Huang, Qiang Zhou, Yici Cai, Haixia Yan:
A thermal-driven force-directed floorplanning algorithm for 3D ICs. CAD/Graphics 2009: 497-502 - [c45]Junjun Gu, Gang Qu, Qiang Zhou:
Information hiding for trusted system design. DAC 2009: 698-701 - [c44]Jinpeng Zhao, Qiang Zhou, Yici Cai:
Fast congestion-aware timing-driven placement for island FPGA. DDECS 2009: 24-27 - [c43]Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou:
Improve clock gating through power-optimal enable function selection. DDECS 2009: 30-33 - [c42]Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia:
Decoupling capacitance efficient placement for reducing transient power supply noise. ICCAD 2009: 745-751 - [c41]Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong:
Cell shifting aware of wirelength and overlap. ISQED 2009: 506-510 - 2008
- [c40]Changdao Dong, Qiang Zhou, Yici Cai, Xianlong Hong:
Wire density driven top-down global placement for CMP variation control. APCCAS 2008: 1676-1679 - [c39]Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian:
Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375 - [c38]Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong:
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL 2008: 559-562 - [c37]Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong:
A novel performance driven power gating based on distributed sleep transistor network. ACM Great Lakes Symposium on VLSI 2008: 255-260 - [c36]Haixia Yan, Qiang Zhou, Xianlong Hong:
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. ISQED 2008: 289-292 - [c35]Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong:
DFM Based Detailed Routing Algorithm for ECP and CMP. ISQED 2008: 357-360 - 2007
- [c34]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang:
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC 2007: 367-372 - [c33]Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong:
Logic and Layout Aware Voltage Island Generation for Low Power Design. ASP-DAC 2007: 666-671 - [c32]Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou:
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925 - [c31]Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong:
Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. CAD/Graphics 2007: 338-343 - [c30]Yanhua Wang, Qiang Zhou, Jinian Bian, Junhua Qu:
VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR. CAD/Graphics 2007: 349-354 - [c29]Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong:
New timing and routability driven placement algorithms for FPGA synthesis. ACM Great Lakes Symposium on VLSI 2007: 570-575 - [c28]Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597 - [c27]Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai:
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. ISCAS 2007: 2040-2043 - [c26]Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou:
Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. ISCAS 2007: 3411-3414 - [c25]Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong:
Power Delivery Aware Floorplanning for Voltage Island Designs. ISQED 2007: 350-355 - [c24]Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai:
Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. ISVLSI 2007: 279-284 - 2006
- [c23]Qiang Zhou, Yi Zou, Yici Cai, Xianlong Hong:
Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. APCCAS 2006: 1635-1638 - [c22]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. ASP-DAC 2006: 582-587 - [c21]Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang:
A novel technique integrating buffer insertion into timing driven placement. ISCAS 2006 - [c20]Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong:
A novel low-power physical design methodology for MTCMOS. ISCAS 2006 - [c19]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185 - 2005
- [c18]Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan:
Analysis of buffered hybrid structured clock networks. ASP-DAC 2005: 93-98 - [c17]Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu:
Clock network minimization methodology based on incremental placement. ASP-DAC 2005: 99-102 - [c16]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Register placement for low power clock network. ASP-DAC 2005: 588-593 - [c15]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating registers in placement for clock network minimization. DAC 2005: 176-181 - [c14]Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou:
Improved multilevel routing with redundant via placement for yield and reliability. ACM Great Lakes Symposium on VLSI 2005: 143-146 - [c13]Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai:
A new algorithm for layout of dark field alternating phase shifting masks. ACM Great Lakes Symposium on VLSI 2005: 221-224 - [c12]Lijuan Luo, Qiang Zhou, Xianlong Hong, Hanbin Zhou:
Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design. ICCSA (4) 2005: 896-905 - [c11]Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu:
A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. ICESS 2005: 275-286 - [c10]Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong:
A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. ICNC (3) 2005: 181-184 - [c9]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
Integrated routing resource assignment for RLC crosstalk minimization. ISCAS (2) 2005: 1871-1874 - [c8]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani:
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233 - [c7]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. PATMOS 2005: 257-266 - 2004
- [c6]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan:
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. ICCD 2004: 344-349 - [c5]Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu:
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) 2004: 81-84 - [c4]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Layer assignment algorithm for RLC crosstalk minimization. ISCAS (5) 2004: 85-88 - [c3]Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai:
Crosstalk driven routing resource assignment. ISCAS (5) 2004: 89-92 - [c2]Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou:
Algorithm for yield driven correction of layout. ISCAS (5) 2004: 241-245 - [c1]Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong:
Shielding area optimization under the solution of interconnect crosstalk. ISCAS (5) 2004: 297-300
Editorship
- 2010
- [e1]Jinian Bian, Qiang Zhou, Peter Athanas, Yajun Ha, Kang Zhao:
Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China. IEEE 2010, ISBN 978-1-4244-8981-7 [contents]
Informal and Other Publications
- 2022
- [i8]Qiang Zhou, Chaohui Yu, Zhibin Wang, Hao Li:
Point RCNN: An Angle-Free Framework for Rotated Object Detection. CoRR abs/2205.14328 (2022) - [i7]Qiang Zhou, Chaohui Yu, Hao Luo, Zhibin Wang, Hao Li:
MimCo: Masked Image Modeling Pre-training with Contrastive Teacher. CoRR abs/2209.03063 (2022) - 2021
- [i6]Qiang Zhou, Chaohui Yu, Chunhua Shen, Zhibin Wang, Hao Li:
Object Detection Made Simpler by Eliminating Heuristic NMS. CoRR abs/2101.11782 (2021) - [i5]Qiang Zhou, Chaohui Yu, Zhibin Wang, Qi Qian, Hao Li:
Instant-Teaching: An End-to-End Semi-Supervised Object Detection Framework. CoRR abs/2103.11402 (2021) - 2020
- [i4]Zhuoqian Yang, Wentao Zhu, Wayne Wu, Chen Qian, Qiang Zhou, Bolei Zhou, Chen Change Loy:
TransMoMo: Invariance-Driven Unsupervised Video Motion Retargeting. CoRR abs/2003.14401 (2020) - 2019
- [i3]Keqiang Sun, Wayne Wu, Tinghao Liu, Shuo Yang, Quan Wang, Qiang Zhou, Zuochang Ye, Chen Qian:
FAB: A Robust Facial Landmark Detection Framework for Motion-Blurred Videos. CoRR abs/1910.12100 (2019) - 2018
- [i2]Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao:
Exploiting Spin-Orbit Torque Devices as Reconfigurable Logic for Circuit Obfuscation. CoRR abs/1802.02789 (2018) - [i1]Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou:
Look at Boundary: A Boundary-Aware Face Alignment Algorithm. CoRR abs/1805.10483 (2018)
Coauthor Index
[j50] [j49] [j48] [j47] [j46] [j45] [j44] [j43] [j42] [j40] [j39] [j37] [j35] [j34] [j33] [j32] [j31] [j29] [j28] [j27] [j26] [j25] [j23] [j20] [j17] [j16] [j15] [j14] [j13] [j12] [j10] [j9] [j8] [j7] [j5] [j4] [j3] [j2] [j1] [c112] [c110] [c108] [c107] [c105] [c104] [c101] [c100] [c99] [c98] [c97] [c96] [c95] [c94] [c93] [c92] [c91] [c90] [c88] [c87] [c86] [c85] [c84] [c82] [c81] [c80] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [c68] [c67] [c66] [c65] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c53] [c51] [c48] [c46] [c44] [c42] [c41] [c40] [c39] [c38] [c37] [c35] [c34] [c33] [c29] [c27] [c25] [c23] [c22] [c21] [c20] [c18] [c17] [c16] [c15] [c14] [c13] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1] [i1]
[j22] [j20] [j18] [j17] [j16] [j15] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [j2] [j1] [c48] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c29] [c28] [c27] [c26] [c25] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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