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"Navigating Register Placement for Low Power Clock Network Design."

Yongqiang Lu et al. (2005)

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DOI: 10.1093/IETFEC/E88-A.12.3405

access: closed

type: Journal Article

metadata version: 2024-02-07

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  - https://dblp.org/rec/journals/ieicet/LuSHZCHH05
Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3405-3411 (2005)

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