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ORCIDIEEE Journal of Solid-State Circuits, Volume 23
Volume 23, Number 1, February 1988
- Masaharu Kubo, Ikuro Masuda, Kenji Miyata, Katsumi Ogiue:
Perspective on BiCMOS VLSIs. 5-11 - Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Katsuhiko Sato, Tsukasa Shirotori, Masakazu Kakuma, Shigeru Morita, Masaaki Kinugawa, Tetsuya Asami, Kazuhito Narita, Jun-Ichi Matsunaga, Akira Higuchi, Mitsuo Isobe, Tetsuya Iizuka:
A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode. 12-19 - Toshio Yamada, Hisakazu Kotani, Junko Matsushima, Michihiro Inoue:
A 4-Mbit DRAM with 16-bit concurrent ECC. 20-26 - Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi:
An experimental large-capacity semiconductor file memory using 16-levels/cell storage. 27-33 - Sang H. Dhong, Nicky Chau-Chun Lu, Wei Hwang, Stephen A. Parke
:
High-speed sensing scheme for CMOS DRAMs. 34-40 - Roy E. Scheuerlein, James D. Meindl:
Offset word-line architecture for scaling DRAMs to the gigabit level. 41-47 - Toshio Takeshima, Masahide Takada, Toshiyuki Shimizu, Takuya Katoh, Mitsuru Sakamoto:
Voltage limiters for DRAMs with substrate-plate-electrode memory cells. 48-52 - Hiroshi Shimada, Shoichiro Kawashima, Hideo Itoh, Noriyuki Suzuki, Takashi Yabu:
A 46-ns 1-Mbit CMOS SRAM. 53-58 - Barbara A. Chappell, Terry I. Chappell, Stanley E. Schuster, Hermann M. Segmuller, James W. Allan, Robert L. Franch, Phillip J. Restle:
Fast CMOS ECL receivers with 100-mV worst-case sensitivity. 59-67 - Takakuni Douseki, Yasuo Ohmori:
BiCMOS circuit technology for a high-speed SRAM. 68-73 - Soo-Ik Chae, James T. Walker, Chong-Cheng Fu, R. Fabian Pease:
Content-addressable memory for VLSI pattern inspection. 74-78 - Syed B. Ali, Barmak Sani, Alex S. Shubat, Keyhan Sinai, Reza Kazerounian, Ching-Jen Hu, Yueh Yale Ma, Boaz Eitan:
A 50-ns 256 K CMOS split-gate EPROM. 79-85 - Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara:
A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM. 86-90 - C. M. Horwitz, M. D. Silver:
Complementary current-mirror logic. 91-97 - Wen-Tai Lin, Jyh-Ping Hwang:
A high-speed shuffle bus for VLSI arrays. 98-104 - Hans Jürgen Mattausch, Fred Matthiesen, Jutta Hartl, Reinhard Tielert, Erwin P. Jacobs:
A memory-based high-speed digital delay line with a large adjustable length. 105-110 - Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Katsuhiko Asada, Hiroaki Terada:
An elastic pipeline mechanism by self-timed circuits. 111-117 - Hideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba:
A DSP line equalizer VLSI for TCM digital subscriber-line transmission. 118-123 - Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, Haruyasu Yamada:
A 32*32-bit multiplier using multiple-valued MOS current-mode circuits. 124-132 - H. Jonathan Chao, Thomas J. Robe, Lanny S. Smoot:
A 140 Mbit/s CMOS LSI framer chip for a broad-band ISDN local access system. 133-141 - Tsutomu Kamoto, Yukio Akazawa, Mitsuru Shinagawa:
An 8-bit 2-ns monolithic DAC. 142-146 - Tomoyuki Watanabe, Kenji Maio, Katsuhiro Norisue, Shin'ichi Hayashi, Seiichi Ueda:
A 400-MHz DA converter with a 4-bit color map for 2000-line display. 147-151 - Hidetoshi Onodera, Tetsuo Tateishi, Keikichi Tamaru:
A cyclic A/D converter that does not require ratio-matched components. 152-158 - Benjamin J. McCarroll, Charles G. Sodini, Hae-Seung Lee:
A high-speed CMOS comparator for use in an ADC. 159-165 - Jacques Assael, Patrice Senn, Mohamed Sameh Tawfik:
A switched-capacitor filter silicon compiler. 166-174 - Hisatoshi Hagiwara, Masazumi Kumazawa, Shigetaka Takagi, Makoto Furihata, Minoru Nagata, Takeshi Yanagisawa:
A monolithic video frequency filter using NIC-based gyrators. 175-182 - Mohammed Ismail, Shirley V. Smith, Richard G. Beale:
A new MOSFET-C universal filter structure for VLSI. 183-194 - Steven L. Garverick, Charles G. Sodini:
A wide-band NMOS balanced modulator/amplifier which uses 1- mu m transistors for linearity. 195-198 - Toshio Kumamoto, Masao Nakaya, Shigeru Kusunoki, Tadashi Nishimura, Nobuharu Yazawa, Yoichi Akasaka, Yasutaka Horiba:
An SOI structure for flash A/D converter. 198-201 - Denny D. Tang, Ching-Te Chuang:
A circuit concept for reducing soft error in high-speed memory cells. 201-203 - Erl-Huei Lu, Lein Harn, Jau-Yien Lee, Wen-Yih Hwang:
A programmable VLSI architecture for computing multiplication and polynomial evaluation modulo a positive integer. 204-207 - Barry W. Johnson, James H. Aylor, Haytham H. Hana:
Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder. 208-215 - Haruyasu Yamada, Ken'ichi Hasegawa, Toshiki Mori, Hiroyuki Sakai, Kunitoshi Aono:
A microprogrammable real-time image processor. 216-223 - Tho Truong Vu, Roderick D. Nelson, Gary M. Lee, Peter C. T. Roberts, Kang W. Lee, Stephen K. Swanson, Andrzej Peczalski, William R. Betten, Steven A. Hanka, Max J. Helix, Peter J. Vold, Gi Young Lee, Stephen A. Jamison, Christopher A. Arsenault, Susan M. Karwoski, Barbara A. Naused, Barry K. Gilbert, Michael S. Shur:
Low-power 2K-cell SDFL gate array and DCFL circuits using GaAs self-aligned E/D MESFETs. 224-238 - Yu-Ying J. Leung, Michael A. Shanblatt:
Simulating the complexity of regular VLSI layout. 239-244 - Ramesh Lohia, Akhtar Ali:
Parametric formulation of CMOS latch-up as a function of chip layout parameters. 245-250 - Eng-Fong Chor, Arthur Brunnschweiler, Peter Ashburn:
A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes. 251-259 - Tomasz Kacprzak:
Analysis of oscillatory metastable operation of an RS flip-flop. 260-266 - Tho Truong Vu, Andrzej Peczalski, Kang W. Lee, Jeff Conger:
The performance of source-coupled FET logic circuits that use GaAs MESFETs. 267-279 - Shih-Lien Lu:
A safe single-phase clocking scheme for CMOS circuits. 280-283 - Edwin V. Jones, Guoan Bi:
Fast up/down counters using identical cascaded modules. 283-285 - Hoon B. Lee, Robert O. Grondin:
A comparison of systolic architectures for matrix multiplication. 285-289 - Igor M. Filanovsky, Ivars G. Finvers:
A simple nonsaturated CMOS multivibrator. 289-292 - Michael J. S. Smith:
On the circuit analysis of the Schmitt trigger. 292-294 - Cormac S. G. Conroy, William A. Lane, Michael A. Moran, Kadaba R. Lakshmikumar, Miles A. Copeland, Robert A. Hadaway:
Comments, with reply, on 'Characterization and modeling of mismatch in MOS transistors for precision analog design'. 294-296
Volume 23, Number 2, April 1988
- Bernward Roessler, Eberhard Wolter:
CMOS analog front end of a transceiver with digital echo cancellation for ISDN. 311-317 - John O. Kolchmeyer, Humberto J. Canal, Elizabeth H. Kissoon-Dunn, Robert D. Howson, Heungsup Park:
A multimode PCM transceiver chip for 1.544-Mbit/s digital telecommunications. 318-322 - Robert R. Cordell:
A 45-Mbit/s CMOS VLSI digital phase aligner. 323-328 - Masaki Hirata, Hachiro Yamada, Hajime Nagai, Kousuke Takahashi:
A versatile data string-search VLSI. 329-335 - Koichi Yamashita, Akinori Kanasugi, Shinpei Hijiya, Gensuke Goto, Nobutake Matsumura, Takehide Shirato:
A wafer-scale 170000-gate FFT processor with built-in test circuits. 336-342 - Richard W. Linderman, Carl G. Shephard, Kent Taylor, Paul W. Coutee, Paul C. Rossbach, James M. Collins, Robert S. Hauser:
A 70-MHz 1.2- mu m CMOS 16-point DFT processor. 343-350 - Bernard Arambepola, Virendra B. Patel, Guy Cheung:
Cascadable one/two-dimensional digital convolver. 351-357 - Nick Kanopoulos, Nagesh Vasanthavada, Robert L. Baker:
Design of an image edge detection filter using the Sobel operator. 358-367 - Randy R. Torrance, Steve P. Sadler, J. Pierre Lamoureux, Jean Lamarche, David J. Frank, Francois Leveille:
The design of a fully integrated graphics system. 368-376 - Andrzej J. Strojwas, Stephen W. Director:
The process engineer's workbench. 377-386 - Michiel A. Beunder, Jürgen Kernhof, Bernd Hoefflinger:
The CMOS gate forest: an efficient and flexible high-performance ASIC design environment. 387-399 - Jyuo-Min Shyu, Alberto L. Sangiovanni-Vincentelli, John P. Fishburn, Alfred E. Dunlop:
Optimization-based transistor sizing. 400-409 - Carl Sechen, Douglas Braun, Alberto L. Sangiovanni-Vincentelli:
ThunderBird: a complete standard cell layout package. 410-420 - Smith Freeman:
Test generation for data-path logic: the F-path method. 421-427 - Prab Varma, Yoshihiro Tohma:
A knowledge-based test generator for standard cell and iterative array logic circuits. 428-436 - Makoto Tsumura, Royozo Takeuchi, Isao Shimizu:
A BiCMOS thermal head intelligent driver with density controllers for full-tone rendition printers. 437-441 - Kurt Mühlemann:
A 30-V row/column driver for flat-panel liquid crystal displays. 442-449 - John K. Moriarty, R. Clifton Jones, Thomas L. Dinkledine:
A serial bus transceiver for the automotive environment. 450-456 - Thomas F. Knight Jr., Alexander Krymm:
A self-terminating low-voltage swing CMOS output driver. 457-464 - Philippe Aubert, Henri J. Oguey, Raymond Vuilleumier:
Monolithic optical position encoder with on-chip photodiodes. 465-473 - Kazuo Kato, Takashi Sase, Hideo Sato, Ichiro Ikushima, Shin'ichi Kojima:
A low-power 128-MHz VCO for monolithic PLL ICs. 474-479 - Michael G. Kane, Philip Y. Chan, Steven S. Cherensky, D. Colin Fowlis:
A 1.5-GHz programmable divide-by-N GaAs counter. 480-484 - Kiyoshi Kajii, Yuu Watanabe, Masahisa Suzuki, Isamu Hanyu, Makoto Kosugi, Kouichiro Odani, Takashi Mimura, Masayuki Abe:
A 40-ps high electron mobility transistor 4.1 K gate array. 485-489 - Masashi Hashimoto, Masayoshi Nomura, Kenji Sasaki, Katsuo Komatsuzaki, Hiroyuki Fujiwara, Takashi Honzawa, Keiichiro Abe, Tadashi Tachibana, Norihisa Kitagawa:
A 20-ns 256 K*4 FIFO memory. 490-499 - Takashi Hotta, Kouzaburou Kurita, Hideo Maejima, Masahiro Iwamura, Shigeya Tanaka, Tadaaki Bandoh, Tatsumi Yamauchi, Atsuo Hotta:
1.3- mu m CMOS/bipolar standard cell library for VLSI computers. 500-506 - Yukihiro Ushiku, Teruo Kobayashi, Akito Yoshida, Nobuyuki Itoh, Akira Nishiyama, Rempei Nakata:
An optimized 1.0- mu m CMOS technology for next-generation channelless gate arrays. 507-513 - Minoru Fujita, Kenji Shiozawa, Tetsurou Kase, Hajime Hayakawa, Fumio Mizuno, Ryo Haruta, Fumio Murai, Shinji Okazaki:
Application and evaluation of direct-write electron beam for ASICs. 514-519 - Floyd E. Anderson, Jenny M. Ford:
A 150 K channelless gate array design in 0.5- mu m CMOS technology. 520-522 - Bruce A. Richman, James E. Hansen, Kelly Cameron:
A deterministic algorithm for automatic CMOS transistor sizing. 522-526 - Robert J. Widlar, Mineo Yamatake:
A monolithic power op amp. 527-535 - Yeong-Sheng Lee, Kenneth W. Martin:
A switched-capacitor realization of multiple FIR filters on a single chip. 536-542 - Simon R. Jones, Ian P. Jalowiecki, Stephen J. Hedge, R. Mike Lea:
A 9-kbit associative memory for high-speed parallel processing applications. 543-548 - David M. Lewis, Brian W. Thomson, Peter I. P. Boulton, E. Stewart Lee:
Transforming bit-serial communication circuits into fast parallel VLSI implementations. 549-557 - Edwin W. Greeneich, Kevin L. McLaughlin:
Analysis and characterization of BiCMOS for high-speed digital logic. 558-565 - Kyo Y. Chung, Gerold W. Neudeck, Harold F. Bare:
Analytical modeling of the CMOS-like a-Si:H TFT inverter circuit. 566-572 - Charles G. Ekroot, Stephen I. Long:
A GaAs 4-bit adder-accumulator circuit for direct digital synthesis. 573-580 - Andrzej Peczalski, Gi Young Lee, William R. Betten, H. Somal, Mark Plagens, James R. Biard, Ian Burrows, Barry K. Gilbert, Rick L. Thompson, Barbara A. Naused, Susan M. Karwoski, Mark L. Samson, Sharon K. Zahn:
A 6 K GaAs gate array with fully functional LSI personalization. 581-590 - Seigo Kotani, Norio Fujimaki, Takeshi Imamura, Shinya Hasuo:
A subnanosecond Josephson 16-bit ALU. 591-596 - Claudio Canali, Manuela Giannini, Andrea Scorzoni, Massimo Vanzi, Enrico Zanoni:
Measurement of the local latch-up sensitivity by means of computer-controller scanning electron microscopy. 597-603 - Yasunobu Nakase, Kenji Anami, Tohru Shiomi, Atsushi Ohba, Shinpei Kayano:
A macro analysis of soft errors in static RAMs. 604-605 - Norman Scheinberg, Robert Bayruns, Ravender Goyal:
A low-frequency GaAs MESFET circuit model. 605-608
Volume 23, Number 3, June 1988
- Jean-Claude Carlach, Pierre Penard, Philippe Quenard, Patrick Renou, Jean-Luc Sicre:
A 1.2.1 post-filter for color-difference interpolation of a MAC video signal. 621-624 - Paul O'Leary, Hans Josef Orben:
10-MHz 64-bit error-tolerant signature recognition circuit. 625-629 - Tony Denayer, Etienne Vanzieleghem, Paul G. A. Jespers:
A class of multiprocessors for real-time image and multidimensional signal processing. 630-638 - Wei Chen, John Mavor, Peter B. Denyer, David Renshaw:
A WSI approach towards defect/fault-tolerant reconfigurable serial systems. 639-646 - Ingrid Verbauwhede, Frank Hoornaert, Joos Vandewalle, Hugo J. De Man:
Security and performance optimization of a new DES data encryption chip. 647-656 - Daijiro Inami, Yoshiaki Kuraishi, Shigeo Fushimi, Yutaka Takahashi, Yasuaki Nukada, Shigeharu Kameyama, Akihiro Shiratori:
An adaptive line equalizer LSI for ISDN subscriber loops. 657-663 - Hans-Martin Rein:
Multi-gigabit-per-second silicon bipolar ICs for future optical-fiber transmission systems. 664-675 - Guy Schou, Joel Cherel, Ernesto H. Perea, Jean-Yves Danckaert, Thierry Dean, Jean Chaplard:
Fully ECL-compatible GaAs standard-cell library. 676-680 - Alain Dubois, Stephane Ruggeri, Guy Schou, Maurice Gloanec, Ernesto H. Perea, Gérard Auvray, Eric Midavaine:
GaAs ICs for high-speed signal processing. 681-687 - Alan F. Murray, Anthony V. W. Smith:
Asynchronous VLSI neural networks using pulse-stream arithmetic. 688-697 - Irmtraud Rugen, Claudia Schrock-Pauli, Martin Gerbershagen:
An interactive layout design system with real-time logical verification and extraction of layout parasitics. 698-704 - Kris Croes, Hugo J. De Man, Paul Six:
CAMELEON: a process-tolerant symbolic layout system. 705-713 - Luc Rijnders, Paul Six, Hugo J. De Man:
Design of a process-tolerant cell library for regular structures using symbolic layout and hierarchical compaction. 714-721 - Stewart G. Smith, Michael Keightley, Peter B. Denyer, Shigenori Nagara:
SECOND: synthesis of elementary circuits on demand. 722-727 - Michiel A. Beunder, Bernd Hoefflinger, Jürgen Kernhof:
New directions in semicustom arrays. 728-735 - Jacques Robert, Philippe Deval:
A second-order high-resolution incremental A/D converter with offset and charge injection compensation. 736-741 - Detlef Daniel, Ulrich Langmann, Berthold G. Bosch:
A silicon bipolar 4-bit 1-Gsample/s full Nyquist A/D converter. 742-749 - François Krummenacher, Norbert Joehl:
A 4-MHz CMOS continuous-time filter with on-chip automatic tuning. 750-758 - Klaas Bult, Hans Wallinga:
A CMOS analog continuous-time delay line with adaptive delay-time control. 759-766 - Reinoud F. Wolffenbuttel:
Digitally programmable accurate current sources for logarithmic control of the amplification or attenuation in a gain cell. 767-773 - Eric A. Vittoz, Marc G. R. Degrauwe, Serge Bitz:
High-performance crystal oscillator circuits: theory and application. 774-783 - Qiuting Huang, Willy M. C. Sansen, Michiel S. J. Steyaert, Peter M. Van Peteghem:
Design and implementation of a CMOS VCXO for FM stereo decoders. 784-793 - Evert Seevinck, Wim De Jager, Piet Buitendijk:
A low-distortion output stage with improved stability for monolithic power amplifiers. 794-801 - Roelof F. Wassenaar, Evert Seevinck, Marinus G. Van Leeuwen, Cornelis J. Speelman, Eerke Holle:
New techniques for high-frequency RMS-to-DC conversion based on a multifunctional V-to-I convertor. 802-815 - W. Pribyl, J. Harter, W. Reczek, D. Sommer, H. Hausele:
CMOS output buffers for megabit DRAMs. 816-819 - Peter H. Saul, M. S. J. Mudd:
A direct digital synthesizer with 100-MHz output capability. 819-821 - Willy M. C. Sansen, Frank Op't Eynde, Michiel Steyaert:
A CMOS temperature-compensated current reference. 821-824https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=322 - A. Koroncai, J. Massoner, Heinz Zitta, Hubert Rothleitner, A. Lechner:
A 69-V CMOS DC/DC converter for ISDN applications. 824-829 - Masayuki Ishikawa, Yukio Tanaka, Tadakatsu Kimura:
An adaptive line equalizer VLSI using digital signal processing. 830-835 - Kazuo Yamakido, Masaru Kokubo, Takahiko Kozaki, Shigeo Nishita, Tatsuya Nishihara, Norio Miyake, Ken'ichi Ohwada:
A subscriber digital signal processor LSI for PCM applications. 836-842 - Joann P. Close, Lewis W. Counts:
A 50-fA junction-isolated operational amplifier. 843-851 - Norio Fujimaki, Takeshi Imamura, Shinya Hasuo:
Josephson pseudorandom bit-sequence generator. 852-858 - Israel Koren, Zahava Koren, Dhiraj K. Pradhan:
Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay. 859-866 - Renuka P. Jindal:
Transimpedance preamplifier with 70-dB AGC range in fine-line NMOS. 867-869 - David V. Kerns Jr.:
Enhanced peaking current reference. 869-872