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2010 – 2019
- 2013
[c34]Marco Cazzaniga
, Patrice Joubert Doriol, Aurora Sanna, Emmanuel Blanc, Valentino Liberali, Davide Pandini:
Evaluating the impact of substrate noise on conducted EMI in automotive microcontrollers. EMC Compo 2013: 129-133- [c33]Andrea Manuzzato, Fabio Campi, Davide Rossi, Valentino Liberali, Davide Pandini:
Exploiting body biasing for leakage reduction: A case study. ISVLSI 2013: 133-138 - [c32]Marco Cazzaniga, Patrice Joubert Doriol, Emmanuel Blanc, Valentino Liberali, Davide Pandini:
Evaluating the impact of substrate on power integrity in industrial microcontrollers. PATMOS 2013: 107-111 - [c31]Andrea Manuzzato, Fabio Campi, Valentino Liberali, Davide Pandini:
Design methodology for low-power embedded microprocessors. PATMOS 2013: 259-264 - 2011
- [c30]Martin Elhøj, André Inácio Reis, Renato P. Ribas, Fabrizio Ferrandi, Christian Pilato, Francesc Moll, Miguel Miranda, Petr Dobrovolný, Nigel Woolaway, Arnaud Grasset, Philippe Bonnot, Giuseppe Desoli, Davide Pandini:
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels. ARCS Workshops 2011 - [c29]Christian Pilato, Fabrizio Ferrandi, Davide Pandini:
Evaluating Static CMOS Complex Cells in Technology Mapping. ARCS Workshops 2011 - [c28]Christian Pilato, Fabrizio Ferrandi, Davide Pandini:
A design methodology for the automatic sizing of standard-cell libraries. ACM Great Lakes Symposium on VLSI 2011: 151-156 - 2010
- [j6]Nikolaos Andrikos, Luciano Lavagno, Fabio Campi, Davide Pandini:
Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization. J. Low Power Electron. 6(4): 607-615 (2010) - [c27]Christian Pilato, Fabrizio Ferrandi, Davide Pandini:
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells. ISVLSI 2010: 23-28
2000 – 2009
- 2009
- [j5]Cristiano Forzan, Davide Pandini:
Statistical static timing analysis: A survey. Integr. 42(3): 409-435 (2009) - [j4]Davide Pandini, Guido A. Repetto, Vincenzo Sinisi:
Clock-tree synthesis for low-EMI design. J. Embed. Comput. 3(3): 197-207 (2009) - [c26]Patrice Joubert Doriol, Yamarita Villavicencio, Cristiano Forzan, Mario Rotigni, Giovanni Graziosi, Davide Pandini:
EMC-aware design on a microcontroller for automotive applications. DATE 2009: 1208-1213 - [c25]Davide Pandini:
Variability in Advanced Nanometer Technologies: Challenges and Solutions. PATMOS 2009: 2 - 2008
- [c24]Paolo Bernardi, Fabio Melchiori, Davide Pandini, Santo Pugliese, Davide Appello:
Robust Design-for-Productization Practices for High Quality Automotive Products. ITC 2008: 1-9 - 2007
- [c23]Nikolaos Andrikos, Luciano Lavagno, Davide Pandini, Christos P. Sotiriou:
A Fully-Automated Desynchronization Flow for Synchronous Circuits. DAC 2007: 982-985 - [c22]Cristiano Forzan, Davide Pandini:
Why we need statistical static timing analysis. ICCD 2007: 91-96 - [c21]Davide Pandini:
Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies. IOLTS 2007: 254 - [c20]Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto:
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. ISVLSI 2007: 92-97 - [c19]Davide Pandini, Guido A. Repetto, Vincenzo Sinisi:
Clock Distribution Techniques for Low-EMI Design. PATMOS 2007: 201-210 - [c18]Davide Pandini:
Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies. PATMOS 2007: 577 - [c17]Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi:
Computing and design for software and silicon manufacturing. VLSI-SoC 2007: 122-127 - [i1]Cristiano Forzan, Davide Pandini:
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis. CoRR abs/0710.4639 (2007) - 2006
- [j3]Cristiano Forzan, Davide Pandini, Mariagrazia Graziano:
Power Supply Selective Mapping for Accurate Timing Analysis. J. Low Power Electron. 2(1): 105-112 (2006) - [c16]Luca Necchi, Luciano Lavagno, Davide Pandini, Laura Vanzago:
An ultra-low energy asynchronous processor for Wireless Sensor Networks. ASYNC 2006: 78-85 - [c15]Davide Pandini, Guido A. Repetto:
Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design. PATMOS 2006: 532-542 - 2005
- [c14]Cristiano Forzan, Davide Pandini:
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis. DATE 2005: 982-983 - [c13]Cristiano Forzan, Davide Pandini:
A complete methodology for an accurate static noise analysis. ACM Great Lakes Symposium on VLSI 2005: 302-307 - [c12]Mariagrazia Graziano, Cristiano Forzan, Davide Pandini:
Power Supply Selective Mapping for Accurate Timing Analysis. PATMOS 2005: 267-276 - [c11]Mariagrazia Graziano, Cristiano Forzan, Davide Pandini:
Including Power Supply Variations into Static Timing Analysis: Methodology and Flow. SoCC 2005: 229-232 - 2004
- [c10]Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini:
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. ACM Great Lakes Symposium on VLSI 2004: 436-439 - [c9]Davide Pandini, Cristiano Forzan, Livio Baldi:
Design Methodologies and Architecture Solutions for High-Performance Interconnects. ICCD 2004: 152-159 - 2003
- [j2]Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Global and local congestion optimization in technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 498-505 (2003) - [c8]Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI 2003: 7-10 - 2002
- [c7]Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Congestion-Aware Logic Synthesis. DATE 2002: 664-671 - [c6]Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Understanding and addressing the impact of wiring congestion during technology mapping. ISPD 2002: 131-136 - 2000
- [c5]Bruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro:
Crosstalk Aware Static Timing Analysis: A Two Step Approach. ISQED 2000: 499-504
1990 – 1999
- 1998
- [c4]Davide Pandini, Primo Scandolara, Carlo Guardiani:
Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs. ASP-DAC 1998: 45-50 - [c3]Bruno Franzini, Cristiano Forzan, Davide Pandini, Y. Liu, Carlo Guardiani:
Nonlinear macromodels of large coupled interconnect networks. CICC 1998: 203-206 - 1995
- [j1]Enrico Malavasi, Davide Pandini:
Optimum CMOS stack generation with analog constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1): 107-122 (1995) - 1994
- [c2]Edoardo Charbon, Enrico Malavasi, Davide Pandini, Alberto L. Sangiovanni-Vincentelli:
Simultaneous Placement and Module Optimization of Analog IC's. DAC 1994: 31-35 - 1993
- [c1]Valentino Liberali, Enrico Malavasi, Davide Pandini:
Automatic Generation of Transistor Stacks for CMOS Analog Layout. ISCAS 1993: 2098-2102
Coauthor Index
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