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ORCIDPeter M. Maurer
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2020 – today
- 2024
[j18]Peter M. Maurer
:
Discrete random variates with finite support using differential search trees. Simul. 100(8): 871-882 (2024)- 2023
- [c35]Peter M. Maurer:
DGL Version 2 - Random Testing in the Mobile Computing Era. SDSC 2023: 172-183 - 2022
- [c34]Peter M. Maurer, John Carbone:
Generating Random XML Files Using DGL. CSCI 2022: 690-694 - [c33]Peter M. Maurer:
Teaching Induction and Deductive Reasoning. CSCI 2022: 2049-2053 - 2021
- [c32]Peter M. Maurer:
Massive Generation of Data with Random Variates. ANNSIM 2021: 1-11 - [c31]Peter M. Maurer:
Computer Science Theory from a Practical Point of View. CSCI 2021: 920-924
2010 – 2019
- 2019
- [c30]Peter M. Maurer:
A nominal/inertial delay metamorphic differential simulator. SummerSim 2019: 10:1-10:10 - 2017
- [c29]Peter M. Maurer:
Finite random variates using differential search trees. SummerSim 2017: 28:1-28:12 - 2016
- [c28]Peter M. Maurer:
Time-parallel multi-delay logic simulation. SpringSim (TMS-DEVS) 2016: 17 - 2015
- [c27]Peter M. Maurer:
Levelized compiled code multi-delay logic simulation. SpringSim (TMS-DEVS) 2015: 33-38 - [c26]Peter M. Maurer:
A second look at oblivious simulation. SummerSim 2015: 55:1-55:6 - 2014
- [c25]Peter M. Maurer:
A universal symmetry detection algorithm. DATE 2014: 1-4 - 2013
- [c24]Peter M. Maurer:
Metamorphic differential simulation using the multi-delay timing model. SpringSim (TMS-DEVS) 2013: 28 - 2012
- [c23]Peter M. Maurer:
Extending symmetric variable-pair transitivities using state-space transformations. ACM Great Lakes Symposium on VLSI 2012: 315-320 - 2011
- [j17]Peter M. Maurer:
Conjugate symmetry. Formal Methods Syst. Des. 38(3): 263-288 (2011)
2000 – 2009
- 2006
- [c22]Peter M. Maurer:
Using conjugate symmetries to enhance gate-level simulations. DATE 2006: 638-643 - 2005
- [j16]Peter M. Maurer:
Converting command-line applications into binary components. Softw. Pract. Exp. 35(8): 787-797 (2005) - [c21]William B. Poucher, Peter M. Maurer:
How to Make Program Assessment Work for You. FECS 2005: 83-87 - 2004
- [j15]Peter M. Maurer:
Metamorphic Programming: Unconventional High Performance. Computer 37(3): 30-38 (2004) - 2003
- [j14]Peter M. Maurer:
Efficient event-driven simulation by exploiting the output observability of gate clusters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1471-1486 (2003) - [c20]Sandeep K. Kondapuram, Peter M. Maurer:
Random Characterization of Design Automation Algorithms. ISVLSI 2003: 264-265 - 2001
- [c19]Allen S. Parrish, Joe Hollingsworth, Peter M. Maurer, Benjamin Shults, Bruce W. Weide:
Identifying an appropriate view of software components for undergraduate education. SIGCSE 2001: 394-395 - 2000
- [j13]Peter M. Maurer:
Components: What If They Gave a Revolution and Nobody Came? Computer 33(6): 28-34 (2000) - [c18]Peter M. Maurer:
Logic Simulation Using Networks of State Machines. DATE 2000: 674-678 - [c17]Peter M. Maurer:
Event Driven Simulation Without Loops or Conditionals. ICCAD 2000: 23-26 - [c16]Peter M. Maurer, William J. Schilp:
State-Machine Based Logic Simulation Using Three Logic Values. VLSI Design 2000: 430-435
1990 – 1999
- 1999
- [c15]Peter M. Maurer, William J. Schilp:
Software Bit-Slicing: A Technique for Improving Simulation Performance. DATE 1999: 786-787 - [c14]Peter M. Maurer:
Efficient Simulation for Hierarchical and Partitioned Circuits. VLSI Design 1999: 236-241 - 1997
- [j12]Peter M. Maurer:
The inversion algorithm for digital simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 762-769 (1997) - 1996
- [j11]Yun Sik Lee, Peter M. Maurer:
Bit-parallel multidelay simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1547-1554 (1996) - [c13]William J. Schilp, Peter M. Maurer:
Unit delay simulation with the inversion algorithm. ICCAD 1996: 412-417 - [c12]Peter M. Maurer:
Is Compiled Simulation Really Faster than Interpreted Simulation? VLSI Design 1996: 303-306 - 1994
- [j10]Peter M. Maurer, Yun Sik Lee:
Gateways: a technique for adding event-driven behavior to compiled simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 338-352 (1994) - [c11]Peter M. Maurer:
The Inversion Algorithm for digital simulation. ICCAD 1994: 258-261 - 1993
- [j9]Peter M. Maurer:
The shadow algorithm: a scheduling technique for both compiled and interpreted simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1411-1413 (1993) - [c10]Yun Sik Lee, Peter M. Maurer:
Parallel multi-delay simulation. ICCAD 1993: 759-762 - 1992
- [j8]Peter M. Maurer:
The Design and Implementation of a Grammar-based Data Generator. Softw. Pract. Exp. 22(3): 223-244 (1992) - [j7]Peter M. Maurer:
Two new techniques for unit-delay compiled simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(9): 1120-1130 (1992) - [c9]Yun Sik Lee, Peter M. Maurer:
Two New Techniques for Compiled Multi-Delay Logic Simulation. DAC 1992: 420-423 - 1991
- [j6]Peter M. Maurer:
Scheduling blocks of hierarchical compiled simulation of combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(2): 184-192 (1991) - 1990
- [j5]Peter M. Maurer:
Dynamic Functional Testing for VLSI Circuits. IEEE Des. Test Comput. 7(6): 42-49 (1990) - [j4]Peter M. Maurer:
Generating Test Data with Enhanced Context-Free Grammars. IEEE Softw. 7(4): 50-55 (1990) - [c8]Peter M. Maurer, Craig D. Morency:
The FHDL PLA tools. ACM Southeast Regional Conference 1990: 3-9 - [c7]Peter M. Maurer:
The FHDL macro processor. ACM Southeast Regional Conference 1990: 10-17 - [c6]Peter M. Maurer, Craig D. Morency:
The FHDL ROM tools. ACM Southeast Regional Conference 1990: 18-24 - [c5]Peter M. Maurer, Zhicheng Wang:
Techniques for Unit-Delay Compiled Simulation. DAC 1990: 480-484 - [c4]Zhicheng Wang, Peter M. Maurer:
LECSIM: A Levelized Event Driven Compiled Logic Simulation. DAC 1990: 491-496 - [c3]Peter M. Maurer:
Optimization of the Parallel Technique for Compiled Unit-Delay Simulation. ICCAD 1990: 70-73
1980 – 1989
- 1989
- [c2]Zhicheng Wang, Peter M. Maurer:
Scheduling High-Level Blocks for Functional Simulation. DAC 1989: 87-90 - 1988
- [j3]Peter M. Maurer:
Design verification of the WE 32106 math accelerator unit. IEEE Des. Test 5(3): 11-21 (1988) - [j2]Peter M. Maurer, Alexander D. Schapira:
A logic-to-logic comparator for VLSI layout verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 897-907 (1988) - [c1]Peter M. Maurer:
Mapping the Data Flow Model of Computation into an Enhanced Von Neumann Processor. ICPP (1) 1988: 235-239 - 1983
- [j1]Peter M. Maurer, Arthur E. Oldehoeft:
The Use of Combinators in Translating A Purely Functional Language to Low-Level Data-Flow Graphs. Comput. Lang. 8(1): 27-45 (1983)
Coauthor Index
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