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ORCIDVishwani D. Agrawal
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2020 – today
- 2024
[j248]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 40(1): 1-2 (2024)- [j247]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 40(2): 137-138 (2024) - [j246]Soham Roy
, Spencer K. Millican, Vishwani D. Agrawal:
A Survey and Recent Advances: Machine Intelligence in Electronic Testing. J. Electron. Test. 40(2): 139-158 (2024) - [j245]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 40(3): 289 (2024) - [j244]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 40(4): 417-418 (2024) - [c227]Soham Roy, Vishwani D. Agrawal:
An Amalgamated Testability Measure Derived from Machine Intelligence. VLSID 2024: 696-701 - 2023
- [j243]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(1): 1-2 (2023) - [j242]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(2): 123 (2023) - [j241]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(3): 263-264 (2023) - [j240]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(4): 403-404 (2023) - [j239]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(5): 535-536 (2023) - 2022
- [j238]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(1): 1-2 (2022) - [j237]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(2): 125-126 (2022) - [j236]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(3): 231 (2022) - [j235]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(4): 335-336 (2022) - [j234]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(5): 463-464 (2022) - [j233]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(6): 575 (2022) - [c226]Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal:
Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits. VTS 2022: 1-7 - 2021
- [j232]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(1): 1-2 (2021) - [j231]Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal:
Estimating Operational Age of an Integrated Circuit. J. Electron. Test. 37(1): 25-40 (2021) - [j230]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(2): 157-158 (2021) - [j229]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(3): 285-286 (2021) - [j228]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(4): 423-424 (2021) - [j227]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(5): 569-570 (2021) - [c225]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Unsupervised Learning in Test Generation for Digital Integrated Circuits. ETS 2021: 1-4 - [c224]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. VLSID 2021: 316-321 - [c223]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits. VTS 2021: 1-14 - [c222]Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal:
Defect Characterization and Testing of Skyrmion-Based Logic Circuits. VTS 2021: 1-7 - 2020
- [j226]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(1): 1-2 (2020) - [j225]Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal:
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures. J. Electron. Test. 36(1): 123-133 (2020) - [j224]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(2): 143-144 (2020) - [j223]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(3): 297-298 (2020) - [j222]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(4): 439-440 (2020) - [j221]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(5): 565-566 (2020) - [j220]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(6): 677-678 (2020) - [c221]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Machine Intelligence for Efficient Test Pattern Generation. ITC 2020: 1-5 - [c220]Vishwani D. Agrawal:
Message from the Steering Committee Chair. VLSID 2020: i - [c219]Yang Sun, Spencer K. Millican, Vishwani D. Agrawal:
Special Session: Survey of Test Point Insertion for Logic Built-in Self-test. VTS 2020: 1-6
2010 – 2019
- 2019
- [j219]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(1): 1-2 (2019) - [j218]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(2): 127-128 (2019) - [j217]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(3): 269-270 (2019) - [j216]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(4): 421-422 (2019) - [j215]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(5): 573 (2019) - [j214]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(6): 761-763 (2019) - [c218]Spencer K. Millican, Yang Sun, Soham Roy, Vishwani D. Agrawal:
Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training. ATS 2019: 13-18 - [c217]Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal:
Improved Random Pattern Delay Fault Coverage Using Inversion Test Points. NATW 2019: 1-6 - [c216]Harshil Goyal, Vishwani D. Agrawal:
Technology Characterization Model and Scaling for Energy Management. VDAT 2019: 679-693 - [c215]Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal:
Two-Pattern ∆IDDQ Test for Recycled IC Detection. VLSID 2019: 82-87 - [c214]Mustafa M. Shihab, Vishwani D. Agrawal:
Energy Efficient Power Distribution on Many-Core SoC. VLSID 2019: 488-493 - [c213]Jubayer Mahmod, Spencer K. Millican, Ujjwal Guin, Vishwani D. Agrawal:
Special Session: Delay Fault Testing - Present and Future. VTS 2019: 1-10 - 2018
- [j213]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(1): 1 (2018) - [j212]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(2): 105 (2018) - [j211]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(3): 209 (2018) - [j210]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(4): 371-372 (2018) - [j209]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(5): 507-508 (2018) - [j208]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(6): 615-617 (2018) - [c212]Ziqi Zhou, Ujjwal Guin, Vishwani D. Agrawal:
Modeling and test generation for combinational hardware Trojans. VTS 2018: 1-6 - 2017
- [j207]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(1): 1-3 (2017) - [j206]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(2): 141 (2017) - [j205]Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling. J. Electron. Test. 33(2): 171-187 (2017) - [j204]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(3): 275 (2017) - [j203]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(4): 377-378 (2017) - [j202]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(5): 539-540 (2017) - [j201]Bei Zhang, Vishwani D. Agrawal:
Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects. J. Electron. Test. 33(5): 573-589 (2017) - [j200]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(6): 689-690 (2017) - 2016
- [j199]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(1): 1-2 (2016) - [j198]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(2): 107-108 (2016) - [j197]Baohu Li, Vishwani D. Agrawal:
Applications of Mixed-Signal Technology in Digital Testing. J. Electron. Test. 32(2): 209-225 (2016) - [j196]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(3): 241-242 (2016) - [j195]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(4): 399 (2016) - [j194]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(5): 505-506 (2016) - [j193]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(6): 653-654 (2016) - [c211]Muralidharan Venkatasubramanian, Vishwani D. Agrawal:
Failures Guide Probabilistic Search for a Hard-to-Find Test. NATW 2016: 18-23 - [c210]Muralidharan Venkatasubramanian, Vishwani D. Agrawal:
Database Search and ATPG - Interdisciplinary Domains and Algorithms. VLSID 2016: 38-43 - 2015
- [j192]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(1): 1-2 (2015) - [j191]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(2): 123 (2015) - [j190]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(3): 225 (2015) - [j189]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(4): 335 (2015) - [j188]Sindhu Gunasekar, Vishwani D. Agrawal:
A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing. J. Electron. Test. 31(4): 403-410 (2015) - [j187]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(5-6): 421-422 (2015) - [j186]Suraj Sindia, Vishwani D. Agrawal:
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. J. Electron. Test. 31(5-6): 479-489 (2015) - [c209]Hejia Liu, Vishwani D. Agrawal:
Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key. ATS 2015: 91-96 - [c208]Muralidharan Venkatasubramanian, Vishwani D. Agrawal, James J. Janaher:
Quest for a quantum search algorithm for testing stuck-at faults in digital circuits. DFTS 2015: 127-132 - [c207]Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal:
Message from the LATS2015 Chairs. LATS 2015: 1 - [c206]Baohu Li, Bei Zhang, Vishwani D. Agrawal:
Adopting multi-valued logic for reduced pin-count testing. LATS 2015: 1-6 - [c205]Harshit Goyal, Vishwani D. Agrawal:
Characterizing Processors for Energy and Performance Management. MTV 2015: 67-72 - [c204]Baohu Li, Vishwani D. Agrawal:
Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing. NATW 2015: 49-54 - [c203]Huiting Zhang, Vishwani D. Agrawal:
SoC TAM Design to Minimize Test Application Time. NATW 2015: 55-60 - [c202]Bei Zhang, Vishwani D. Agrawal:
Diagnostic Tests for Pre-bond TSV Defects. VLSID 2015: 387-392 - [c201]Sindhu Gunasekar, Vishwani D. Agrawal:
Few Good Frequencies for Power-Constrained Test. VLSID 2015: 393-398 - 2014
- [j185]Bei Zhang, Vishwani D. Agrawal:
A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs. J. Electron. Test. 30(1): 57-75 (2014) - [j184]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(2): 155-156 (2014) - [j183]Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
A Test Time Theorem and its Applications. J. Electron. Test. 30(2): 229-236 (2014) - [j182]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(3): 251-252 (2014) - [j181]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(4): 383-384 (2014) - [j180]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(5): 491-492 (2014) - [j179]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(6): 637-638 (2014) - [j178]Yu Zhang, Bei Zhang, Vishwani D. Agrawal:
Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools. J. Electron. Test. 30(6): 763-780 (2014) - [j177]Karthik Naishathrala Jayaraman, Vishwani D. Agrawal:
A Four-Transistor Level Converter for Dual-Voltage Low-Power Design. J. Low Power Electron. 10(4): 617-628 (2014) - [c200]Bei Zhang, Vishwani D. Agrawal:
An optimized diagnostic procedure for pre-bond TSV defects. ICCD 2014: 189-194 - [c199]Suraj Sindia, Vishwani D. Agrawal:
Specification test minimization for given defect level. LATW 2014: 1-6 - [c198]Sindhu Gunasekar, Vishwani D. Agrawal:
Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock. NATW 2014: 52-56 - [c197]Muralidharan Venkatasubramanian, Vishwani D. Agrawal:
A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation. NATW 2014: 57-60 - 2013
- [j176]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(1): 1-2 (2013) - [j175]Ozgur Sinanoglu, Vishwani D. Agrawal:
Eliminating the Timing Penalty of Scan. J. Electron. Test. 29(1): 103-114 (2013) - [j174]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(2): 121 (2013) - [j173]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(3): 255 (2013) - [j172]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(4): 453 (2013) - [j171]Suraj Sindia, Vishwani D. Agrawal:
Neural Network Guided Spatial Fault Resilience in Array Processors. J. Electron. Test. 29(4): 473-483 (2013) - [j170]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(5): 617 (2013) - [j169]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(6): 741-742 (2013) - [j168]Mridula Allani, Vishwani D. Agrawal:
Energy-Efficient Dual-Voltage Design Using Topological Constraints. J. Low Power Electron. 9(3): 275-287 (2013) - [c196]Bei Zhang, Baohu Li, Vishwani D. Agrawal:
Yield analysis of a novel wafer manipulation method in 3D stacking. 3DIC 2013: 1-8 - [c195]Suraj Sindia, Vishwani D. Agrawal:
High sensitivity test signatures for unconventional analog circuit test paradigms. ITC 2013: 1-10 - [c194]Praveen Venkataramani, Vishwani D. Agrawal:
ATE test time reduction using asynchronous clock period. ITC 2013: 1-10 - [c193]Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
A test time theorem and its applications. LATW 2013: 1-5 - [c192]Chidambaram Alagappan, Vishwani D. Agrawal:
Defect Diagnosis of Digital Circuits Using Surrogate Faults. VDAT 2013: 376-386 - [c191]Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Power-aware SoC test optimization through dynamic voltage and frequency scaling. VLSI-SoC 2013: 102-107 - [c190]Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages. VLSI Design 2013: 267-272 - [c189]Praveen Venkataramani, Vishwani D. Agrawal:
Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. VLSI Design 2013: 273-278 - [c188]Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
Finding best voltage and frequency to shorten power-constrained test time. VTS 2013: 1-6 - 2012
- [j167]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(1): 1 (2012) - [j166]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(2): 151-152 (2012) - [j165]Mohammed Ashfaq Shukoor, Vishwani D. Agrawal:
Diagnostic Test Set Minimization and Full-Response Fault Dictionary. J. Electron. Test. 28(2): 177-187 (2012) - [j164]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(3): 263-264 (2012) - [j163]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(4): 389-390 (2012) - [j162]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. J. Electron. Test. 28(4): 541-549 (2012) - [j161]