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Publication search results
found 160 matches
- 2005
- Aniket, Ravishankar Arunachalam:
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. VLSI Design 2005: 479-484 - Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan:
ADOPT: An Approach to Activity Based Delay Optimization. VLSI Design 2005: 411-416 - Muhammad Arsalan, Maitham Shams:
Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits. VLSI Design 2005: 171-174 - Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury:
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. VLSI Design 2005: 255-260 - Sudarshan Bahukudumbi, Krishna Bharath:
A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores. VLSI Design 2005: 804-807 - Falguni Bala, Tapas Nandy:
Conventional RC oscillators, though offer inexpensiveProgrammable High Frequency RC Oscillator. VLSI Design 2005: 511-515 - G. Josemin Bala, J. Raja Paul Perinbam:
A Novel Low Power 16X16 Content Addressable Memory Using PA. VLSI Design 2005: 791-794 - Shibaji Banerjee, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury:
Computer Aided Test (CAT) Tool for Mixed Signal SOCs. VLSI Design 2005: 787-790 - Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar:
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. VLSI Design 2005: 579-585 - Arindam Basu, Anindya Sundar Dhar:
Design Issues in Switched Capacitor Ladder Filters. VLSI Design 2005: 862-865 - Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti:
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules. VLSI Design 2005: 213-218 - Shabbir H. Batterywala, Madhav P. Desai:
Variance Reduction in Monte Carlo Capacitance Extraction. VLSI Design 2005: 85-90 - Luca Benini, Sandeep K. Shukla, Rajesh K. Gupta:
Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems. VLSI Design 2005: 18-20 - Janick Bergeron:
Modeling Usable and Reusable Transactors in System Verilog. VLSI Design 2005: 36- - Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan:
Memory-Centric Motion Estimator. VLSI Design 2005: 816-819 - Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design 2005: 586-591 - K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti:
A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. VLSI Design 2005: 207-212 - M. S. Bhat, H. S. Jamadagni:
Power Optimization in Current Mode Circuits. VLSI Design 2005: 175-180 - A. B. Bhattacharyya:
Compact MOSFET Models for Low Power Analog CMOS Design. VLSI Design 2005: 15 - Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim, Thomas Chen:
A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems. VLSI Design 2005: 124-129 - R. D. (Shawn) Blanton, Subhasish Mitra:
Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. VLSI Design 2005: 8-9 - Shekhar Borkar:
VLSI Design Challenges for Gigascale Integration. VLSI Design 2005: 27 - Pradip Bose:
Power-Aware, Reliable Microprocessor Design. VLSI Design 2005: 3-6 - Charlie Brej, Jim D. Garside:
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. VLSI Design 2005: 368-373 - Paul Capewell, Ian Watson:
A RISC Hardware Platform for Low Power Java. VLSI Design 2005: 138-143 - Krishnendu Chakrabarty:
Design, Testing, and Applications of Digital Microfluidics-Based Biochips. VLSI Design 2005: 221-226 - Avik Chakraborty:
Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays. VLSI Design 2005: 249-254 - Kameshwar Chandrasekar, Michael S. Hsiao:
Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs. VLSI Design 2005: 189-194 - Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney:
Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits. VLSI Design 2005: 336-341 - Abhijit Chatterjee, Ali Keshavarzi, Amit Patra, Siddhartha Mukhopadhyay:
Test Methodologies in the Deep Submicron Era - Analog, Mixed-Signal, and RF. VLSI Design 2005: 12-13
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