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ORCIDSrivaths Ravi 0001
Person information
- affiliation: Texas Instruments Bangalore, India
Other persons with the same name
- S. Ravi 0002
![[0000-0002-2071-1550]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-2071-1550")
(aka: Srivaths Ravi 0002) — Kavery Engineering College, Salem, India (and 1 more)
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2020 – today
- 2023
[j37]Isaac Bruce, Praise O. Farayola, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing. J. Electron. Test. 39(1): 57-69 (2023)- 2022
- [j36]Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing. J. Electron. Test. 38(6): 637-651 (2022) - [c77]Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing. DFT 2022: 1-6 - [c76]Abraham Steenhoek, Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Graph Theory Approach for Multi-site ATE Board Parameter Extraction. ETS 2022: 1-2 - [c75]Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing. ITC 2022: 509-513 - [c74]Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing. VTS 2022: 1-7 - 2021
- [j35]Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Detection of Site to Site Variations From Volume Measurement Data in Multisite Semiconductor Testing. IEEE Trans. Instrum. Meas. 70: 1-12 (2021) - [c73]Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation. DTIS 2021: 1-6 - [c72]Isaac Bruce, Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study. ETS 2021: 1-4 - [c71]Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Systematic Hardware Error Identification and Calibration for Massive Multisite Testing. ITC 2021: 304-308 - 2020
- [c70]Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Quantile - Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing. VTS 2020: 1-6
2010 – 2019
- 2017
- [c69]V. Prasanth, David Foley, Srivaths Ravi:
Demystifying automotive safety and security for semiconductor developer. ITC 2017: 1-10 - [c68]Yiorgos Makris, Srivaths Ravi, Amit Majumdar:
Foreword. VTS 2017: 1-2 - 2015
- [c67]Prabhat Mishra, Swarup Bhunia, Srivaths Ravi:
Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems. VLSID 2015: 3-5 - 2014
- [c66]Chandan Kumar, Fadi Maamari, Kiran Vittal, Wilson Pradeep, Rajesh Tiwari, Srivaths Ravi:
Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs. ATS 2014: 125-130 - [c65]Raashid Shaikh, Pradeep Wilson, Khushboo Agarwal, H. V. Sanjay, Rajesh Tiwari, Kaushik Lath, Srivaths Ravi:
At-speed capture power reduction using layout-aware granular clock gate enable controls. ITC 2014: 1-10 - [c64]Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula:
Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. VLSID 2014: 5-6 - 2011
- [j34]Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi:
Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. J. Low Power Electron. 7(4): 502-515 (2011) - [c63]Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi:
Multi-CoDec Configurations for Low Power and High Quality Scan Test. VLSI Design 2011: 370-375 - 2010
- [c62]Abhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe:
Methodology for early and accurate test power estimation at RTL. ITC 2010: 813 - [c61]Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji:
A generic low power scan chain wrapper for designs using scan compression. VTS 2010: 135-140
2000 – 2009
- 2009
- [j33]George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi:
Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. J. Low Power Electron. 5(1): 58-68 (2009) - 2008
- [j32]Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena:
Low Power Test for Nanometer System-on-Chips (SoCs). J. Low Power Electron. 4(1): 81-100 (2008) - [j31]Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi:
Systematic Software-Based Self-Test for Pipelined Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1441-1453 (2008) - [c60]Khushboo Agarwal, Srinivas Vooka, Srivaths Ravi, Rubin A. Parekhji, Arjun Singh Gill:
Power Analysis and Reduction Techniques for Transition Fault Testing. ATS 2008: 403-408 - [c59]Anish Muttreja, Srivaths Ravi, Niraj K. Jha:
Variability-Tolerant Register-Transfer Level Synthesis. VLSI Design 2008: 621-628 - [c58]Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji:
A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. VTS 2008: 53-58 - 2007
- [j30]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Automated Energy/Performance Macromodeling of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 542-552 (2007) - [j29]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Hybrid Simulation for Energy Estimation of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1843-1854 (2007) - [j28]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2035-2045 (2007) - [j27]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy-optimizing source code transformations for operating system-driven embedded software. ACM Trans. Embed. Comput. Syst. 7(1): 2:1-2:26 (2007) - [j26]Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 15(3): 296-308 (2007) - [j25]Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee:
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 465-470 (2007) - [j24]Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Architectural Support for Run-Time Validation of Program Data Properties. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 546-559 (2007) - [j23]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha:
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 605-609 (2007) - [j22]Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 699-710 (2007) - [j21]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1191-1204 (2007) - [c57]Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Energy and execution time analysis of a software-based trusted platform module. DATE 2007: 1128-1133 - [c56]Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji:
Methodology for low power test pattern generation using activity threshold control logic. ICCAD 2007: 526-529 - [c55]Srivaths Ravi:
Power-aware test: Challenges and solutions. ITC 2007: 1-10 - [c54]Srivaths Ravi, Stefan Mangard:
Tutorial T1: Designing Secure SoCs. VLSI Design 2007: 3 - [i1]Joel Coburn, Srivaths Ravi, Anand Raghunathan:
Hardware Accelerated Power Estimation. CoRR abs/0710.4742 (2007) - 2006
- [j20]Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 544-557 (2006) - [j19]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1589-1602 (2006) - [j18]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Use of Computation-Unit Integrated Memories in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1969-1989 (2006) - [j17]Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
RTL-Aware Cycle-Accurate Functional Power Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2103-2117 (2006) - [j16]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2193-2206 (2006) - [j15]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. IEEE Trans. Mob. Comput. 5(2): 128-143 (2006) - [j14]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Scalable Synthesis Methodology for Application-Specific Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1175-1188 (2006) - [j13]Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1295-1308 (2006) - [c53]Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Architectural support for safe software execution on embedded processors. CODES+ISSS 2006: 106-111 - [c52]Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi:
Systematic software-based self-test for pipelined processors. DAC 2006: 393-398 - [c51]Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC 2006: 496-501 - [c50]Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Architectures for efficient face authentication in embedded systems. DATE Designers' Forum 2006: 1-6 - [c49]Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee:
Satisfiability-based framework for enabling side-channel attacks on cryptographic software. DATE Designers' Forum 2006: 18-23 - [c48]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Active Learning Driven Data Acquisition for Sensor Networks. ISCC 2006: 929-934 - [c47]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha:
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. VLSI Design 2006: 299-304 - [c46]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. VLSI Design 2006: 473-476 - 2005
- [j12]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Generation of distributed logic-memory architectures through high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1694-1711 (2005) - [c45]Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
SECA: security-enhanced communication architecture. CASES 2005: 78-89 - [c44]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory. CICC 2005: 239-242 - [c43]Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Enhancing security through hardware-assisted run-time validation of program data properties. CODES+ISSS 2005: 190-195 - [c42]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Hybrid simulation for embedded software energy estimation. DAC 2005: 23-26 - [c41]Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Efficient fingerprint-based user authentication for embedded systems. DAC 2005: 244-247 - [c40]Joel Coburn, Srivaths Ravi, Anand Raghunathan:
Power emulation: a new paradigm for power estimation. DAC 2005: 700-705 - [c39]Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. DATE 2005: 178-183 - [c38]Joel Coburn, Srivaths Ravi, Anand Raghunathan:
Hardware Accelerated Power Estimation. DATE 2005: 528-529 - [c37]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70 - [c36]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. VLSI Design 2005: 551-556 - 2004
- [j11]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 216-228 (2004) - [j10]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A hybrid energy-estimation technique for extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 652-664 (2004) - [j9]Srivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady:
Security in embedded systems: Design challenges. ACM Trans. Embed. Comput. Syst. 3(3): 461-491 (2004) - [c35]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Automated energy/performance macromodeling of embedded software. DAC 2004: 99-102 - [c34]Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan:
Security as a new dimension in embedded system design. DAC 2004: 753-760 - [c33]Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Power estimation for cycle-accurate functional descriptions of hardware. ICCAD 2004: 668-675 - [c32]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
High-level synthesis using computation-unit integrated memories. ICCAD 2004: 783-790 - [c31]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. VLSI Design 2004: 261-266 - [c30]Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Tamper Resistance Mechanisms for Secure, Embedded Systems. VLSI Design 2004: 605- - 2003
- [c29]Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey:
A scalable software-based self-test methodology for programmable processors. DAC 2003: 548-553 - [c28]Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater:
Securing Mobile Appliances: New Challenges for the System Designer. DATE 2003: 10176-10183 - [c27]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy Estimation for Extensible Processors. DATE 2003: 10682-10687 - [c26]Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi:
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. DATE 2003: 10706-10713 - [c25]Indradeep Ghosh, Srivaths Ravi:
On automatic generation of RTL validation test benches using circuit testing techniques. ACM Great Lakes Symposium on VLSI 2003: 289-294 - [c24]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ICCAD 2003: 46-53 - [c23]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Scalable Application-Specific Processor Synthesis Methodology. ICCAD 2003: 283-290 - [c22]Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ICCD 2003: 187-193 - [c21]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Analyzing the energy consumption of security protocols. ISLPED 2003: 30-35 - [c20]Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Embedding Security in Wireless Embedded Systems. VLSI Design 2003: 269-270 - [c19]Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Efficient RTL Power Estimation for Large Designs. VLSI Design 2003: 431-439 - 2002
- [j8]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
High-level test compaction techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 827-841 (2002) - [j7]Srivaths Ravi, Niraj K. Jha:
Test synthesis of systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1211-1217 (2002) - [c18]Jacob Chang, Srivaths Ravi, Anand Raghunathan:
FLEXBAR: A crossbar switching fabric with improved performance and utilization. CICC 2002: 405-408 - [c17]Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass:
System design methodologies for a wireless security processing platform. DAC 2002: 777-782 - [c16]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana:
Optimizing public-key encryption for wireless clients. ICC 2002: 1050-1056 - [c15]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
High-level synthesis of distributed logic-memory architectures. ICCAD 2002: 564-571 - [c14]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of custom processors based on extensible platforms. ICCAD 2002: 641-648 - [c13]Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys:
Special Session: Security on SoC. ISSS 2002: 192-194 - [c12]Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi:
Securing Wireless Data: System Architecture Challenges. ISSS 2002: 195-200 - 2001
- [j6]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
Testing of core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 426-439 (2001) - [j5]Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha:
Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1414-1425 (2001) - [j4]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 824-832 (2001) - [c11]Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana:
Transient Power Management Through High Level Synthesis. ICCAD 2001: 545-552 - [c10]Srivaths Ravi, Niraj K. Jha:
Fast test generation for circuits with RTL and gate-level views. ITC 2001: 1068-1077 - [c9]Srivaths Ravi, Niraj K. Jha:
Synthesis of System-on-a-chip for Testability. VLSI Design 2001: 149-156 - 2000
- [j3]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 894-906 (2000) - [j2]Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana:
Integrating variable-latency components into high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1105-1117 (2000) - [c8]Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana:
A Technique for Identifying RTL and Gate-Level Correspondences. ICCD 2000: 591-594 - [c7]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
: Reducing test application time in high-level test generation. ITC 2000: 829-838 - [c6]Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana:
High-Level Synthesis with Variable-Latency Components. VLSI Design 2000: 220-227
1990 – 1999
- 1999
- [c5]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
A framework for testing core-based systems-on-a-chip. ICCAD 1999: 385-390 - [c4]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS 1999: 398-406 - 1998
- [j1]Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. J. Electron. Test. 13(2): 201-212 (1998) - [c3]