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2020 – today
- 2020
[j55]Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay:
A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection. Integr. 74: 93-106 (2020)- [j54]Priyajit Mukherjee, Navonil Chatterjee, Santanu Chattopadhyay:
Thermal-aware detour routing in 3D NoCs. J. Parallel Distributed Comput. 144: 230-245 (2020) - [j53]Ajay Khare, Chinmay Patil, Santanu Chattopadhyay:
Task mapping and flow priority assignment of real-time industrial applications for network-on-chip based design. Microprocess. Microsystems 77: 103175 (2020) - [j52]Rajit Karmakar
, Santanu Chattopadhyay, Rohit Kapur:
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 546-550 (2020) - [c92]Rajit Karmakar, Santanu Chattopadhyay:
A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access. DATE 2020: 448-453 - [c91]Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya:
A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing. ISDCS 2020: 1-6 - [c90]Rajit Karmakar, Santanu Chattopadhyay:
On Securing Scan Obfuscation Strategies Against ScanSAT Attack. ISQED 2020: 213-218 - [c89]Rajit Karmakar, Santanu Chattopadhyay:
Hardware IP Protection Using Logic Encryption and Watermarking. ITC 2020: 1-10
2010 – 2019
- 2019
- [j51]Kanchan Manna, Chatla Swami Sagar, Santanu Chattopadhyay, Indranil Sengupta:
Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems. ACM J. Emerg. Technol. Comput. Syst. 15(1): 6:1-6:27 (2019) - [j50]Priyajit Mukherjee, Kokil Jain, Santanu Chattopadhyay:
Thermal-aware task allocation and scheduling for periodic real-time applications in mesh-based heterogeneous NoCs. Real Time Syst. 55(4): 774-809 (2019) - [c88]Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya:
Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach. ICIT 2019: 228-233 - [c87]Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay:
A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis. DAC 2019: 90 - [c86]Rajit Karmakar, Santanu Chattopadhyay, Mrityunjoy Chakraborty:
Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure. ISCAS 2019: 1-5 - [c85]Ajay Khare, Irene Anna Boben, Santanu Chattopadhyay:
Enhanced Schedulability via Minimal Routing with Mapping and Priority Assignment for Real-Time Network-on-chip. TENCON 2019: 564-568 - [c84]Kaushik Khatua, Hillol Maity, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya:
A Deep Neural Network Augmented Approach for Fixed Polarity AND-XOR Network Synthesis. TENCON 2019: 2189-2193 - [i2]N. Prasad, Navonil Chatterjee, Santanu Chattopadhyay, Indrajit Chakrabarti:
Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip. CoRR abs/1908.00289 (2019) - 2018
- [j49]Priyajit Mukherjee, Sandeep D'Souza, Santanu Chattopadhyay:
Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution. Integr. 60: 167-189 (2018) - [j48]Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay:
Reliability-aware application mapping onto mesh based Network-on-Chip. Integr. 62: 92-113 (2018) - [j47]N. Prasad, Priyajit Mukherjee, Santanu Chattopadhyay, Indrajit Chakrabarti:
Design and evaluation of ZMesh topology for on-chip interconnection networks. J. Parallel Distributed Comput. 113: 17-36 (2018) - [j46]Navonil Chatterjee, Suraj Paul, Santanu Chattopadhyay:
Task mapping and scheduling for network-on-chip based multi-core platform with transient faults. J. Syst. Archit. 83: 34-56 (2018) - [j45]Kanchan Manna, Priyajit Mukherjee, Santanu Chattopadhyay, Indranil Sengupta:
Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design. IEEE Trans. Computers 67(4): 528-542 (2018) - [j44]N. Prasad, Indrajit Chakrabarti, Santanu Chattopadhyay:
An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3543-3554 (2018) - [c83]Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay:
On Finding Suitable Key-Gate Locations In Logic Encryption. ISCAS 2018: 1-5 - [c82]Raghav Sonavane, Gobburi Sai Kashyap, Santanu Chattopadhyay:
Thermal Aware Application Mapping and Frequency Scaling for Mesh-Based Network-On-Chip Design. iSES 2018: 70-75 - [c81]Ajay Khare, Chinmay Patil, Manikanta Nallamalli, Santanu Chattopadhyay:
Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC. VDAT 2018: 433-445 - [i1]Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur:
Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits. CoRR abs/1801.04961 (2018) - 2017
- [j43]Rajit Karmakar, Santanu Chattopadhyay:
Temperature and data size trade-off in dictionary based test data compression. Integr. 57: 20-33 (2017) - [j42]Priyajit Mukherjee, Santanu Chattopadhyay:
Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design. Integr. 58: 167-188 (2017) - [j41]Soumya J., K. Niranjan Babu, Santanu Chattopadhyay:
Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture. J. Circuits Syst. Comput. 26(11): 1750174:1-1750174:31 (2017) - [j40]Navonil Chatterjee, Suraj Paul, Priyajit Mukherjee, Santanu Chattopadhyay:
Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform. J. Syst. Archit. 74: 61-77 (2017) - [j39]Navonil Chatterjee, Suraj Paul, Santanu Chattopadhyay:
Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform. ACM Trans. Embed. Comput. Syst. 16(4): 108:1-108:24 (2017) - [c80]N. Prasad, Rajit Karmakar, Santanu Chattopadhyay, Indrajit Chakrabarti:
Runtime mitigation of illegal packet request attacks in Networks-on-Chip. ISCAS 2017: 1-4 - [c79]Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur:
Enhancing security of logic encryption using embedded key generation unit. ITC-Asia 2017: 131-136 - [c78]Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta:
A New Logic Encryption Strategy Ensuring Key Interdependency. VLSI Design 2017: 429-434 - 2016
- [j38]Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Small Test Set Generation with High Diagnosability. J. Circuits Syst. Comput. 25(4): 1650024:1-1650024:18 (2016) - [j37]Sandeep D'Souza, Soumya J., Santanu Chattopadhyay:
Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels. ACM Trans. Archit. Code Optim. 12(4): 40:1-40:26 (2016) - [j36]Kanchan Manna, Shivam Swami, Santanu Chattopadhyay, Indranil Sengupta:
Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design. ACM Trans. Embed. Comput. Syst. 16(1): 24:1-24:25 (2016) - [j35]Bibhas Ghoshal, Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta:
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 393-397 (2016) - [c77]Kanchan Manna, Chatla Swamy Sagar, Santanu Chattopadhyay, Indranil Sengupta:
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs. ISVLSI 2016: 529-534 - [c76]Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta:
Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip. ISVLSI 2016: 583-586 - [c75]Navonil Chatterjee, Sheshivardhan Reddy, Shilpa Reddy, Santanu Chattopadhyay:
A reliability aware application mapping onto mesh based Network-on-Chip. RAIT 2016: 537-542 - [c74]Priyajit Mukherjee, Santanu Chattopadhyay:
An ILP-based floorplan-aware path synthesis technique for Application-Specific NoC design. RAIT 2016: 543-548 - [c73]Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay:
A strategy for fault tolerant reconfigurable Network-on-Chip design. VDAT 2016: 1-2 - [c72]Rajit Karmakar, Santanu Chattopadhyay:
Thermal-Safe Schedule Generation for System-on-Chip Testing. VLSI Design 2016: 475-480 - [c71]Srinivasa Shashank Nuthakki, Rajit Karmakar, Santanu Chattopadhyay, Krishnendu Chakrabarty:
Optimization of the IEEE 1687 access network for hybrid access schedules. VTS 2016: 1-6 - 2015
- [j34]Kanchan Manna, Chakradhar Reddy Veeramreddy, Santanu Chattopadhyay, Indranil Sengupta:
Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation. Int. J. High Perform. Syst. Archit. 5(3): 141-152 (2015) - [j33]Rajit Karmakar, Santanu Chattopadhyay:
Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling. Integr. 50: 61-73 (2015) - [j32]Pradip Kumar Sahu, Kanchan Manna, Tapan Shah, Santanu Chattopadhyay:
A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip. J. Circuits Syst. Comput. 24(8): 1550126:1-1550126:29 (2015) - [j31]Soumya J., Srijan Tiwary, Santanu Chattopadhyay:
Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores. J. Syst. Archit. 61(1): 1-11 (2015) - [j30]Soumya J., Kundan Kumar, Santanu Chattopadhyay:
Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes. J. Syst. Archit. 61(9): 410-422 (2015) - [j29]N. Prasad, Santanu Chattopadhyay, Indrajit Chakrabarti:
Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip. Microprocess. Microsystems 39(8): 741-751 (2015) - [j28]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1185-1195 (2015) - [c70]Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay:
Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints. ATS 2015: 73-78 - [c69]Srinivasa Shashank Nuthakki, Santanu Chattopadhyay:
An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets. ATS 2015: 151-156 - [c68]Navonil Chatterjee, Santanu Chattopadhyay:
Fault tolerant mesh based Network-on-Chip architecture. ISCAS 2015: 417-420 - [c67]Arpita Dutta, Subhadip Kundu, Santanu Chattopadhyay, Bijit Kumar Das:
A hardware based low temperature solution for VLSI testing using decompressor side masking. ISCAS 2015: 637-640 - [c66]Srinivasa Shashank Nuthakki, Santanu Chattopadhyay, Mrityunjoy Chakraborty:
Test set customization for improved fault diagnosis without sacrificing coverage. ISCAS 2015: 1574-1577 - [c65]N. Prasad, Santanu Chattopadhyay, Indrajit Chakrabarti:
ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms. iNIS 2015: 146-151 - [c64]Kanchan Manna, Vadapalli Shanmukha Sri Teja, Santanu Chattopadhyay, Indranil Sengupta:
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning. ISVLSI 2015: 392-397 - [c63]Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
GA based diagnostic test pattern generation for transition faults. VDAT 2015: 1-6 - [c62]Santanu Chattopadhyay:
Power- and thermal-aware testing of VLSI circuits and systems. VDAT 2015: 1 - [c61]Sandeep D'Souza, Soumya J., Santanu Chattopadhyay:
A constructive heuristic for application mapping onto an express channel based Network-on-Chip. VDAT 2015: 1-6 - [c60]Arpita Dutta, Santanu Chattopadhyay:
Particle swarm optimization approach for low temperature BIST. VDAT 2015: 1-6 - [c59]Rajit Karmakar, Santanu Chattopadhyay:
Thermal-Aware Test Data Compression Using Dictionary Based Coding. VLSI Design 2015: 53-58 - [c58]Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay:
Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach. VTS 2015: 1-6 - 2014
- [j27]Pradip Kumar Sahu, Kanchan Manna, Nisarg Shah, Santanu Chattopadhyay:
Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip. J. Syst. Archit. 60(7): 562-578 (2014) - [j26]Soumya J., Ashish Sharma, Santanu Chattopadhyay:
Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 7(2): 7:1-7:24 (2014) - [j25]Pradip Kumar Sahu, Tapan Shah, Kanchan Manna, Santanu Chattopadhyay:
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 300-312 (2014) - [j24]Subhadip Kundu, Aniket Jha, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 696-700 (2014) - [c57]Navonil Chatterjee, Santanu Chattopadhyay, Kanchan Manna:
A spare router based reliable Network-on-Chip design. ISCAS 2014: 1957-1960 - [c56]Navonil Chatterjee, N. Prasad, Santanu Chattopadhyay:
A spare link based reliable Network-on-Chip design. VDAT 2014: 1-6 - [c55]Soumya J., Ashish Sharma, Santanu Chattopadhyay:
A locally reconfigurable Network-on-Chip architecture and application mapping onto it. VDAT 2014: 1-6 - [c54]Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay:
Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model. VDAT 2014: 1-6 - [c53]Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta:
Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip. VLSI-SoC 2014: 1-6 - [c52]Santanu Chattopadhyay:
Tutorial T7A: Techniques for Network-on-Chip (NoC) Design and Test. VLSI Design 2014: 16-17 - 2013
- [j23]Pradip Kumar Sahu, Santanu Chattopadhyay:
A survey on application mapping strategies for Network-on-Chip design. J. Syst. Archit. 59(1): 60-76 (2013) - [j22]Soumya J., Santanu Chattopadhyay:
Application-Specific Network-on-Chip synthesis with flexible router Placement. J. Syst. Archit. 59(7): 361-371 (2013) - [j21]Subhadip Kundu, Sankhadeep Pal, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
A Metric for Test Set Characterization and Customization Toward Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1824-1828 (2013) - [c51]Arpita Dutta, Subhadip Kundu, Santanu Chattopadhyay:
Thermal Aware Don't Care Filling to Reduce Peak Temperature and Thermal Variance during Testing. Asian Test Symposium 2013: 25-30 - [c50]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
An ATE assisted DFD technique for volume diagnosis of scan chains. DAC 2013: 31:1-31:6 - [c49]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Aggresive scan chain masking for improved diagnosis of multiple scan chain failures. ETS 2013: 1 - [c48]Kanchan Manna, Shailesh Singh, Santanu Chattopadhyay, Indranil Sengupta:
Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization. VDAT 2013: 74-82 - 2012
- [j20]A. Mitra, Santanu Chattopadhyay:
Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique. IET Comput. Digit. Tech. 6(6): 353-361 (2012) - [j19]Subhadip Kundu, Santanu Chattopadhyay:
Efficient don't care filling and scan chain masking for low-power testing. Int. J. Comput. Aided Eng. Technol. 4(2): 101-125 (2012) - [j18]S. Krishna Kumar, Subhadip Kundu, Santanu Chattopadhyay:
Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing. Integr. 45(2): 211-221 (2012) - [j17]Sambhu Nath Pradhan, Santanu Chattopadhyay:
Multiplexer-Based Multi-Level Circuit Synthesis with Area-Power Trade-Off. J. Circuits Syst. Comput. 21(5) (2012) - [j16]Santanu Kundu, Soumya J., Santanu Chattopadhyay:
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router. Microprocess. Microsystems 36(6): 471-488 (2012) - [c47]Tapas Kumar Maiti, Subhadip Kundu, Arpita Dutta, Santanu Chattopadhyay:
Confidence Based Power Aware Testing. ISED 2012: 62-66 - [c46]Pradip Kumar Sahu, Ashish Sharma, Santanu Chattopadhyay:
Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization. ISED 2012: 172-176 - [c45]Rekha Govindaraj, Indranil Sengupta, Santanu Chattopadhyay:
An Efficient Technique for Longest Prefix Matching in Network Routers. VDAT 2012: 317-326 - [c44]Bibhas Ghoshal, Subhadip Kundu, Indranil Sengupta, Santanu Chattopadhyay:
Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip. VDAT 2012: 343-349 - [c43]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection. VLSI Design 2012: 436-441 - [e1]Hafizur Rahaman, Sanatan Chattopadhyay, Santanu Chattopadhyay:
Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings. Lecture Notes in Computer Science 7373, Springer 2012, ISBN 978-3-642-31493-3 [contents] - 2011
- [j15]Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay:
Low power finite state machine synthesis using power-gating. Integr. 44(3): 175-184 (2011) - [j14]Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay:
And-or-XOR Network Synthesis with Area-Power Trade-Off. J. Circuits Syst. Comput. 20(6): 1019-1035 (2011) - [c42]Pradip Kumar Sahu, Putta Venkatesh, Sunilraju Gollapalli, Santanu Chattopadhyay:
Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization. ISVLSI 2011: 335-336 - [c41]Soumya J., Putta Venkatesh, Santanu Chattopadhyay:
Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis. ISVLSI 2011: 341-342 - [c40]Santanu Kundu, Santanu Chattopadhyay:
Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits. ISVLSI 2011: 357-358 - [c39]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. VLSI Design 2011: 364-369 - 2010
- [c38]S. Krishna Kumar, S. Kaundinya, Santanu Chattopadhyay:
Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing. Asian Test Symposium 2010: 401-406 - [c37]S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay:
Customizing pattern set for test power reduction via improved X-identification and reordering. ISLPED 2010: 177-182
2000 – 2009
- 2009
- [j13]Saurabh Chaudhury, Krishna Teja Sistla, Santanu Chattopadhyay:
Genetic algorithm-based FSM synthesis with area-power trade-offs. Integr. 42(3): 376-384 (2009) - [j12]Saurabh Chaudhury, J. Srinivasa Rao, Santanu Chattopadhyay:
State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis. J. Low Power Electron. 5(4): 464-473 (2009) - [c36]Subhadip Kundu, Santanu Chattopadhyay:
Efficient Don't Care Filling for Power Reduction during Testing. ARTCom 2009: 319-323 - [c35]S. Krishna Kumar, P. Uday Bhaskar, Santanu Chattopadhyay, Pradip Mandal:
Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing. ARTCom 2009: 346-350 - [c34]Santanu Kundu, Kanchan Manna, Shobhit Gupta, Kundan Kumar, Ritesh Parikh, Santanu Chattopadhyay:
A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic. ARTCom 2009: 414-418 - [c33]Subhadip Kundu, S. Krishna Kumar, Santanu Chattopadhyay:
Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption. Asian Test Symposium 2009: 307-312 - [c32]Ajit Pal, Santanu Chattopadhyay:
Synthesis & Testing for Low Power. VLSI Design 2009: 37-38 - 2008
- [j11]Santanu Kundu, Santanu Chattopadhyay:
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology. Int. J. High Perform. Syst. Archit. 1(3): 163-182 (2008) - [c31]Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay:
Three-level AND-OR-XOR network synthesis: A GA based approach. APCCAS 2008: 574-577 - [c30]Santanu Kundu, Santanu Chattopadhyay:
Mesh-of-tree deterministic routing for network-on-chip architecture. ACM Great Lakes Symposium on VLSI 2008: 343-346 - [c29]Mayur Bubna, Naresh Shenoy, Santanu Chattopadhyay:
An efficient greedy approach to PLA folding. ISCAS 2008: 1356-1359 - [c28]Rafiahamed Shaik, Mrityunjoy Chakraborty, Santanu Chattopadhyay:
An efficient finite precision realization of the block adaptive decision feedback equalizer. ISCAS 2008: 1910-1913 - [c27]Tapas K. Maiti, Santanu Chattopadhyay:
Don't care filling for power minimization in VLSI circuit testing. ISCAS 2008: 2637-2640 - [c26]Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay:
Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. ISVLSI 2008: 269-274 - 2007
- [c25]Chandan Giri, Dilip Kumar Reddy Tipparthi, Santanu Chattopadhyay:
Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling. ICCTA 2007: 141-145 - [c24]Chandan Giri, B. Mallikarjuna Rao, Santanu Chattopadhyay:
Test Data Compression by Spilt-VIHC (SVIHC). ICCTA 2007: 146-150 - [c23]Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay:
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach. ICIC (2) 2007: 1032-1041 - [c22]Chandan Giri, Santanu Chattopadhyay:
Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs. ISCAS 2007: 3679-3682 - [c21]Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay:
A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs. VLSI-SoC 2007: 320-323 - 2006
- [c20]Saurabh Chaudhury, Santanu Chattopadhyay, J. Srinivasa Rao:
Synthesis of Finite State Machines for Low Power and Testability. APCCAS 2006: 1434-1437 - 2005
- [j10]Santanu Chattopadhyay:
Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis?A Genetic Algorithm Approach. Comput. J. 48(4): 443-450 (2005) - [c19]Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay:
Flip-flop chaining architecture for power-efficient scan during test application. Asian Test Symposium 2005: 410-413 - [c18]